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Version 1.0
Page 13 of 44
SMT370v2 User Manual
Figure 2 - CommPort interface data path.
S
undance
H
igh-speed
B
us.
buses are identical and 60-bit wide.
SHBs
are parallel communication links for synchronous transmissions. Each
SHB
can be divided into two independent 8-bit buses. Each 8-bit bus includes a clock and
three control signals: write enable, request and acknowledge. An
SHB
bus can also
be divided into two 16-bit buses and one 8-bit bus.
Here is the architecture of the
SHB
interface implemented into the FPGA:
D[0..31]
FIFO
256 x 32 x 2
D[0..15]
Control Logic and Status
CLK WEN REQ ACK
SHB A
DATA
Figure 3 - SHB interface structure.
SMT370 communication links.
The
SMT370
provides 2 CommPort links. They are given the numbers 0 and 3. The
default firmware provided with the board implements CommPort3 as a control
register communication port, which means that every control register word has to be
sent to CommPort3 on the
SMT370
to be received.
The board also connects two full
SHB
connectors (60 bits) to the FPGA. The FPGA
implements two 16-bit (or one 32-bit) unidirectional interfaces per
SHB
connector:
output only for SHBA – used to send out samples coming from both ADCs - and input
only for SHBB – used to suck samples in to the DAC.