Sundance Spas PXIe-700, Руководство пользователя

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PXIe-700 User Guide
Page 12
Rev. 1.7
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email: sales@sundancedsp.com
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2016.
A
PPENDIX
4.1 Pinout
4.1.1 PXIe
This board conforms to PXIe specification.
J2:
973028 from ERNI backplane connector. This is used to provide PCIe signals from PXIe
host to the board.
Note: The control signals are connected to 1.8v Bank (LVCMOS_18). All the differential signals
are LVDS signals.
PIN A
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 B
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 C
1 P AD18 AD18 PXIe_CLK- AE18 AE18 GND
2 PRSNT# PWREN GND
3 SMBDAT M29 M29 SMBCLK M28 M28 GND
4 MPWRGD PERST# AH19 AH19 GND
5 1PETP0 Y2 Y2 1PETN0 Y1 Y1 GND
6 1PETP2 U4 U4 1PETN2 U3 U3 GND
7 1PETP3 T2 T2 1PETN3 T1 T1 GND
8 1PETP5 1PETN5 GND
9 1PETP6 1PETN6 GND
10 RSV RSV GND
PIN D
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 E
FPGA_PIN
Rev 3.0
FPGA_PIN
Rev 4.0 F
1 PX AF17 AD17 PXIe_SYNC- AG17 AD16 GND
2 PXIe AH17 AH17 PXIe_DSTARB- AJ17 AJ17 GND
3 RSV RSV GND
4 RSV RSV GND
5 1PERP0 AA4 AA4 1PERN0 AA3 AA3 GND
6 1PERP2 W4 W4 1PERN2 W3 W3 GND
7 1PERP3 V6 V6 1PERN3 V5 V5 GND
8 1PERP5 1PERN5 GND
9 1PERP6 1PERN6 GND
10 RSV RSV GND