Sun Microsystems SPARCengine Ultra AXi, Техническое руководство

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4-2 SPARCengine Ultra AX i OEM Technical Manual • May 1999
TABLE 4-1
Power Up Sequence
Phase Description Observation
Power-Connected
Rear switch ON When Power is connected, +5V SB power will be
present. This Stand By power is available to the front
panel power switch circuitry. No fan rotation, no LED
Illumination.
The Front Panel
ON-OFF switch is
pressed Power_On signal is driven to activate the power
supply. All the outputs appear. The power supply
verifies the outputs have reached the nominal value
(output sequence applies) and drives the Power_OK
signal. The fan in the power supply starts.
The hard disk and CD-ROM devices
self-initialize.
POWER OK signal
generates RESET
signal.
Pressing RESET
button generates
RESET signal
All chips and the CPU module are brought to an
initialized state. The PCI cards also receive this
signal to initialize their internal state. The SCSI
devices and the floppy drive may also initialize
using this signal.
The CPU starts executing the instructions from the
Flash memory
Minimum required hardware registers initialized. The power LED will illuminate.
CPU clock speed is also determined and re-initialized.
Probe for keyboard entry to skip POST.
Execute POST. POST messages appear on TTYA
console
Probe for amount of installed memory on four banks.
Decompress and copy ROM/OBP code into RAM.
Probe keyboard. LED’s on keyboard blink.
Either keyboard or enclosure
speaker will beep.
Probe for amount of installed memory on four banks.
Graphic display device installed. Banner displayed
Execute NVRAMRC.
Probe FFB.
Probe PCIB, Ethernet interface, Ebus
Probe PCIB slot J2001.
Probe PCIB slot J2002