7. Block Diagram:
G1
G2
MAIN_L
MAIN_R
EFX
AUX
PFL\AFL_DET
PFL
G-1 OUT
G-2 OUT
G-1
ASSIGN
TO
L/R
LEFT
OUT
RIGHT
OUT
G-2
ASSIGN
TO
L/R
G-1
MAIN_R
MAIN_L
EFX
AUX
PFL
PFL_DET
G-2
PFL_DET
PFL
AUX
EFX
MAIN_L
MAIN_R
G-1
G-2
G-1
G-2
PFL_DET
PFL
MAIN_L
MAIN_R
MAIN_L
MAIN_R
PFL_DET
PFL
G-1
G-2
MAIN_L
MAIN_R
G1
G2
MAIN_L
MAIN_R
EFX
AUX
PFL\AFL_DET
PFL
G-1
G-2
EFX SEND
EFX OUTPUT
EFX
PFL_DET
PFL
MAIN_L
MAIN_R
AUX
EFX SEND
TO
DSP
PROCESSOR
FS MUTE
24 bit DSP
PROCESSOR
L
R
AUX SEND
AFL
AFL/PFL
AFL
U+
U+
AFL
POWER
MAIN
AC
INPUT
7
Содержание Aqua 10
Страница 11: ...9 9 Notes ...