Hardware layout and configuration
UM1521
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Doc ID 022868 Rev 1
2.12 Serial
EEPROM
A 4 Kbit (M95040-R) serial EEPROM is connected to SPI1 of the STM32L152ZDT6.
Serial Flash chip select is managed by I/O pin PB0.
The EEPROM will work properly when VDD > 1.8 V.
The LCD glass module has to be mounted on IO position for SPI EEPROM usage. Refer to
for detail.
2.13 RF
EEPROM
The RF EEPROM daughterboard (MB1020) implemented on the module is the M24LR64-R.
This EEPROM can be accessed by the MCU via the I2C bus or by RF using a 13.56 MHz
reader (for instance CR95HF).
The daughterboard can be connected to the STM32L152ZDT6 via the I2C bus on CN2.
The I2C address of RF EEPROM is 0b1010E2E1E0. E0-E2 values are determined by the
RF EEPROM daughterboard.
The RF EEPROM will work properly when VDD > 1.8 V.
The LCD glass module has to be mounted on IO position for RF EEPROM usage. Refer to
for detail.
2.14 SRAM
512Kx16-bit SRAM is connected to bank2 of the FSMC interface and both 8-bit and 16-bit
accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM respectively.
The SRAM will work properly when VDD > 2.4 V.
The LCD glass module has to be mounted on IO position for SRAM usage. Refer to
for detail.
2.15 NOR
Flash
128 Mbit NOR Flash is connected to bank1 of the FSMC interface. The 16-bit operation
mode is selected by pull-up resister connected to BYTE pin of NOR Flash. Write protection
is enabled or disabled by jumper JP9.
The LCD glass module has to be mounted on IO position for NOR Flash usage. Refer to
for detail.
Table 16.
NOR Flash related jumpers
Jumper
Description
JP9
Write protection is enabled when JP9 is fitted while write protection is disabled when JP9 is
not fitted.
Default setting
: Not fitted
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