STMicroelectronics EVALSPEAr320CPU, Руководство пользователя

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Figure 6. DDR interface schematic
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
4 4
3 3
2 2
1 1
Spear300 CPU Board
2.3 DDR2 interface
2 8
20 Oct 2009
Place close to pin Place close to pin
Place close to pin
Place close to pin
Place close to DDR2 Chip Place close to DDR2 Chip
Place close to LAST DDR2 Chip
Place close to pins
nCAS
nCS0
DQS0
DQS1
DQM0
DQM1
BA0
BA1
BA2
CLK_EN
CLK
nCLK
nCS0
nDQS0
nDQS1
nRAS
nWE
ODT0
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
VREF
ODT0
DATA0
DATA1
DATA2
DATA3
DATA5
DATA9
DATA7
ADDR10
ADDR11
ADDR12
ADDR13
DATA4
DATA6
DATA11
DATA15
DATA13
DATA10
DATA8
DATA14
DATA12
DATA6
DATA15
DATA10
DATA11
DATA2
DATA12
DATA7
DATA4
DATA8
DATA9
DATA1
DATA0
DATA13
DATA14
DATA3
DATA5
ADDR1
ADDR3
ADDR4
ADDR5
ADDR6
ADDR11
ADDR7
ADDR12
ADDR8
ADDR13
ADDR9
ADDR0
ADDR10
ADDR2
BA2
BA1
BA0
nCS1
nWE
nCAS
nRAS
nCLK
CLK_EN
CLK
ODT1
DQS1
nDQS1
nDQS0
DQS0
DQM0
DQM1
nCLK VREF CLK
DATA7
DATA10
DATA15
DATA14
DATA1
DATA9
DATA6
DATA5
DATA13
DATA12
DATA2
DATA3
DATA8
DATA11
DATA0
DATA4
ADDR1
ADDR3
ADDR4
ADDR5
ADDR6
ADDR11
ADDR7
ADDR12
ADDR8
ADDR13
ADDR9
ADDR0
ADDR10
ADDR2
BA2
BA1
BA0
nWE
nCAS
nRAS
nCLK
CLK_EN
CLK
DQS1
nDQS1
nDQS0
DQS0
DQM0
DQM1
nCS1
ODT1
DATA[0..15]
ADDR[0..13]
VREF VREF
VREF
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP
1.8V_SP 1.8V_SP
Rev
Date: Sheet
of
Board
Title
Code
Project
Rev
Date: Sheet
of
Board
Title
Code
Project
Rev
Date: Sheet
of
Board
Title
Code
Project
C7
0.
1 uF
X5R
10V
C7
0.
1 uF
X5R
10V
C19
0.
1 uF
X5R
10V C19
0.
1 uF
X5R
10V
C62
10 uF X5R 10V C62
10 uF X5R 10V
R9
470 Ohm R9
470 Ohm
M
IC
R
ON DDR
2
8
M
B
x16 M
T
47H64M
16HR
-3
U2
MT47H64M16HR3,NC
M
IC
R
ON DDR
2
8
M
B
x16 M
T
47H64M
16HR
-3
U2
MT47H64M16HR3,NC
DATA0
G8
DATA1
G2
DATA2
H7
DATA3
H3
DATA4
H1
DATA5
H9
DATA6
F1
DATA7
F9
DATA8
C8
DATA9
C2
DATA10
D7
DATA11
D3
DATA12
D1
DATA13
D9
DATA14
B1
DATA15
B9
ADDR0
M8
ADDR1
M3
ADDR2
M7
ADDR3
N2
ADDR4
N8
ADDR5
N3
ADDR6
N7
ADDR7
P2
ADDR8
P8
ADDR9
P3
ADDR10
M2
ADDR11
P7
ADDR12
R2
ADDR13
R8
UDM
B3
LDM
F3
VREF
J2
CKE
K2
nWE
K3
BA0
L2
BA1
L3
BA2
L1
nUDQS
A8
UDQS
B7
nLDQS
E8
LDQS
F7
CLK
J8
nCLK
K8
nRAS
K7
nCAS
L7
nCS
L8
ODT
K9
RFU2
R7
RFU1
R3
NC2
A2
NC1
E2
VDD1V8_1
A1
VDD1V8_2
E1
VDD1V8_3
M9
VDD1V8_4
R1
VDD1V8_5
J9
VDDL1V8
J1
VDDQ1V8_1
A9
VDDQ1V8_2
C1
VDDQ1V8_3
C3
VDDQ1V8_4
C7
VDDQ1V8_5
C9
VDDQ1V8_7
G1
VDDQ1V8_8
G3
VDDQ1V8_9
G7
VDDQ1V8_10
G9
VSS5
A3
VSS4
E3
VSS3
J3
VSS2
N1
VSS1
P9
VSSDL
J7
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VDDQ1V8_6
E9
C10
0.
1 uF
X5R
10V
C10
0.
1 uF
X5R
10V
C8
0.
1 uF
X5R
10V
C8
0.
1 uF
X5R
10V
R2
100 Ohm R2
100 Ohm
C13
0.
1 uF
X5R
10V
C13
0.
1 uF
X5R
10V
R1
121 Kohm 1%
R1
121 Kohm 1%
C12
0.
1 uF
X5R
10V
C12
0.
1 uF
X5R
10V
REF7
FIDUCIAL
REF7
FIDUCIAL
C1
0.
1 uF
X5R
10V
C1
0.
1 uF
X5R
10V
R5
100 Ohm R5
100 Ohm
C14
0.
1 uF
X5R
10V
C14
0.
1 uF
X5R
10V
REF8
FIDUCIAL
REF8
FIDUCIAL
C11
0.
1 uF
X5R
10V C11
0.
1 uF
X5R
10V
R3
100 Ohm R3
100 Ohm
C15
0.
1 uF
X5R
10V
C15
0.
1 uF
X5R
10V
C20
0.
1 uF
X5R
10V
C20
0.
1 uF
X5R
10V
REF1
FIDUCIAL
REF1
FIDUCIAL
C6
0.
1 uF
X5R
10V
C6
0.
1 uF
X5R
10V
TP30
TP_diff
TP30
TP_diff
1
1
2
2
C16
0.
1 uF
X5R
10V
C16
0.
1 uF
X5R
10V
C2
0.1 uF X5R 10V
C2
0.1 uF X5R 10V
REF2
FIDUCIAL
REF2
FIDUCIAL
R4
100 Ohm R4
100 Ohm
C18
0.
1 uF
X5R
10V
C18
0.
1 uF
X5R
10V
C4
0.1 uF X5R 10V C4
0.1 uF X5R 10V
M
IC
R
ON DDR
2
8
M
B
x16 M
T
47H64M
16HR
-3
U3
MT47H64M16HR3
M
IC
R
ON DDR
2
8
M
B
x16 M
T
47H64M
16HR
-3
U3
MT47H64M16HR3
DATA0
G8
DATA1
G2
DATA2
H7
DATA3
H3
DATA4
H1
DATA5
H9
DATA6
F1
DATA7
F9
DATA8
C8
DATA9
C2
DATA10
D7
DATA11
D3
DATA12
D1
DATA13
D9
DATA14
B1
DATA15
B9
ADDR0
M8
ADDR1
M3
ADDR2
M7
ADDR3
N2
ADDR4
N8
ADDR5
N3
ADDR6
N7
ADDR7
P2
ADDR8
P8
ADDR9
P3
ADDR10
M2
ADDR11
P7
ADDR12
R2
ADDR13
R8
UDM
B3
LDM
F3
VREF
J2
CKE
K2
nWE
K3
BA0
L2
BA1
L3
BA2
L1
nUDQS
A8
UDQS
B7
nLDQS
E8
LDQS
F7
CLK
J8
nCLK
K8
nRAS
K7
nCAS
L7
nCS
L8
ODT
K9
RFU2
R7
RFU1
R3
NC2
A2
NC1
E2
VDD1V8_1
A1
VDD1V8_2
E1
VDD1V8_3
M9
VDD1V8_4
R1
VDD1V8_5
J9
VDDL1V8
J1
VDDQ1V8_1
A9
VDDQ1V8_2
C1
VDDQ1V8_3
C3
VDDQ1V8_4
C7
VDDQ1V8_5
C9
VDDQ1V8_7
G1
VDDQ1V8_8
G3
VDDQ1V8_9
G7
VDDQ1V8_10
G9
VSS5
A3
VSS4
E3
VSS3
J3
VSS2
N1
VSS1
P9
VSSDL
J7
VSSQ1
A7
VSSQ2
B2
VSSQ3
B8
VSSQ4
D2
VSSQ5
D8
VSSQ6
E7
VSSQ7
F2
VSSQ8
F8
VSSQ9
H2
VSSQ10
H8
VDDQ1V8_6
E9
C5
0.
1 uF
X5R
10V
C5
0.
1 uF
X5R
10V
S
p
ear300
DDR2 Interface
U1B
Spear300
S
p
ear300
DDR2 Interface
U1B
Spear300
DATA0
P11
DATA1
R11
DATA2
T11
DATA3
U11
DATA4
T12
DATA5
R12
DATA6
P12
DATA7
P13
DATA8
T17
DATA9
T16
DATA10
U17
DATA11
U16
DATA12
U14
DATA13
U13
DATA14
T13
DATA15
R13
ADDR0
T2
ADDR1
T1
ADDR2
U1
ADDR3
U2
ADDR4
U3
ADDR5
U4
ADDR6
U5
ADDR7
T5
ADDR8
R5
ADDR9
P5
ADDR10
P6
ADDR11
R6
ADDR12
T6
ADDR13
U6
ADDR14
R7
nRAS
U8
nCAS
T8
nWE
T7
nCS0
P9
nCS1
R9
DQS0
U10
nDQS0
T10
nDQS1
T15
DQS1
U15
ODT0
T3
ODT1
T4
GATE_OPEN0
R10
GATE_OPEN1
R14
DQM0
U12
DQM1
T14
BA0
P7
BA1
P8
BA2
R8
CLK
T9
nCLK
U9
CLK_EN
U7
VREF
P10
COMP_2V5_REXT
P4
COMP_2V5_GND
R4
C17
0.
1 uF
X5R
10V
C17
0.
1 uF
X5R
10V
R8
470 Ohm R8
470 Ohm
C3
0.
1 uF
X5R
10V
C3
0.
1 uF
X5R
10V
C9
0.
1 uF
X5R
10V
C9
0.
1 uF
X5R
10V
C99
0.1 uF X5R 10V
C99
0.1 uF X5R 10V
C61
10 uF X5R 10V C61
10 uF X5R 10V
FB1
WUR
T
H 742792023
FB1
WUR
T
H 742792023
FB2
WUR
T
H 742792023
FB2
WUR
T
H 742792023
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