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Schematics
DocID030
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Figure 30. 32L4R9IDISCOVERY PSRAM
11
14
PSRAM
MB1311
C
28/08/2017
Title:
Size:
Reference:
Date:
Sheet:
of
A4
Revision:
STM32L4R9I-DISCO
Project:
Synchronous PSRAM
PSRAM_D[0..15]
PSRAM_A[0..20]
PSRAM
PSRAM_A[0..20]
PSRAM_NE1
PSRAM_NBL0
PSRAM_WE
PSRAM_OE
PSRAM_D[0..15]
PSRAM_NBL1
PSRAM_WAIT
PSRAM_CLK
PSRAM_ADV
PSRAM
PSRAM_NE1
PSRAM_NBL0
PSRAM_NBL1
PSRAM_WE
PSRAM_OE
PSRAM_NBL0
PSRAM_NBL1
PSRAM_WE
PSRAM_OE
PSRAM_A0
PSRAM_A1
PSRAM_A2
PSRAM_A3
PSRAM_A4
PSRAM_A5
PSRAM_A6
PSRAM_A7
PSRAM_A8
PSRAM_A9
PSRAM_A10
PSRAM_A11
PSRAM_A12
PSRAM_A13
PSRAM_A14
PSRAM_A15
PSRAM_A16
PSRAM_A17
PSRAM_A18
PSRAM_D0
PSRAM_D1
PSRAM_D2
PSRAM_D3
PSRAM_D4
PSRAM_D5
PSRAM_D6
PSRAM_D7
PSRAM_D8
PSRAM_D9
PSRAM_D10
PSRAM_D11
PSRAM_D12
PSRAM_D13
PSRAM_D14
PSRAM_D15
PD5
PD4
PD14
PD15
PD0
PD1
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PD8
PD9
PD10
PF0
PF1
PF2
PF3
PF4
PF5
PF12
PF13
PF14
PF15
PG0
PG1
PD11
PD12
PD13
PG2
PG3
PG4
PG5
PE0
PE1
functional at 3.3V only
PSRAM_NE1
100nF
C16
100nF
C14
SB5
R17
0
JP2
+3V3
PSRAM_VDD
PSRAM_VDD
PSRAM_VDD
VDD_LCD
0
R13
R11
[N/A]
PSRAM_A0
PSRAM_A1
PSRAM_A2
PSRAM_A3
PSRAM_A4
PSRAM_A5
PSRAM_A6
PSRAM_A7
PSRAM_A8
PSRAM_A9
PSRAM_A10
PSRAM_A11
PSRAM_A12
PSRAM_A13
PSRAM_A14
PSRAM_A15
PSRAM_A16
PSRAM_A17
PSRAM_A18
PF0
PF1
PF2
PF3
PF4
PF5
PF12
PF13
PF14
PF15
PG0
PG1
PD11
PD12
PD13
PG2
PG3
PG4
PG5
PSRAM_D0
PSRAM_D1
PSRAM_D2
PSRAM_D3
PSRAM_D4
PSRAM_D5
PSRAM_D6
PSRAM_D7
PSRAM_D8
PSRAM_D9
PSRAM_D10
PSRAM_D11
PSRAM_D12
PSRAM_D13
PSRAM_D14
PSRAM_D15
PD14
PD15
PD0
PD1
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PD8
PD9
PD10
PSRAM_NBL0
PSRAM_NBL1
PSRAM_WE
PSRAM_OE
PD5
PD4
PE0
PE1
PSRAM_CE_CS1
SB3
PSRAM_A20
CRE_CS2
VDD_VDDQ
VDD_VDDQ
H6
Asynchronous PSRAM
3.3V I/Os only
PSRAM_CLK
PSRAM_ADV
PSRAM_WAIT
PSRAM_CLK
PSRAM_ADV
PSRAM_WAIT
SB3 and SB4 are only useful for U6 :
Double footprint for Async/Sync PSRAMs compatibility
i
PSRAM_A
Matched Net Lengths [ Tolerance = 200 mil ]
Impedance Constraint [Min = 40 Max = 60 ]
i PSRAM_D
Matched Net Lengths [ Tolerance = 200 mil ]
Impedance Constraint [Min = 40 Max = 60 ]
i
PSRAM_A
i
PSRAM_A i
PSRAM_A i
PSRAM_A i
PSRAM_A
i
PSRAM_A
i
PSRAM_A
i
PSRAM_D
PSRAM_CE_CS1
PD3
PD6
PB7
PD7
PSRAM_A19
PE4
SB4
H6
PSRAM_VDD
PE3
A4
B4
A3
B3
A2
A5
A1
A4
A0
A3
CS1
B5
I/O0
B6
I/O1
C5
I/O2
C6
I/O3
D5
VDD
D6
GND
D1
I/O4
E5
I/O5
F5
I/O6
F6
I/O7
G6
WE
G5
A16
E4
A15
F4
A14
F3
A13
G4
A12
G3
A11
H5
A10
H4
A9
H3
A8
H2
I/O8
B1
I/O9
C1
I/O10
C2
I/O11
D2
VDD
E1
I/O12
E2
I/O13
F2
I/O14
F1
I/O15
G1
LB
A1
UB
B2
OE
A2
A7
D4
A6
C4
A5
C3
A17
D3
A18
H1
GND
E6
CS2
A6
NC
E3
NC
H6
IS66WV1M16EBLL-55BLI
A19
G2
U5
PSRAM_A19
PE3
IS66WVC2M16ECLL-7010BLI
A4
B4
A3
B3
A2
A5
A1
A4
A0
A3
CE
B5
I/O0
B6
I/O1
C5
I/O2
C6
I/O3
D5
VDD
D6
VSSQ
D1
I/O4
E5
I/O5
F5
I/O6
F6
I/O7
G6
WE
G5
A16
E4
A15
F4
A14
F3
A13
G4
A12
G3
A11
H5
A10
H4
A9
H3
A8
H2
I/O8
B1
I/O9
C1
I/O10
C2
I/O11
D2
VDDQ
E1
I/O12
E2
I/O13
F2
I/O14
F1
I/O15
G1
LB
A1
UB
B2
OE
A2
A7
D4
A6
C4
A5
C3
A17
D3
A18
H1
VSS
E6
CRE
A6
NC
J6
NC
E3
NC
J4
A19
G2
A20
H6
WAIT
J1
CLK
J2
ADV
J3
NC
J5
U6
[N/A]
SB3
U5 used
U6 used
X
SB4
X
R8
R9
R10
R12
[N/A]
10K
10K
10K
[N/A]
10K
10K
10K
[N/A]
0R
0R
[N/A]
If SB3 is fitted, CAMERA and PSRAM functions are exclusives; if SB4 fitted, PSRAM usable memory density is reduced to 16M bits
(Default)
10K
R10
10K
R9
10K
R8
10K
[N/A]
R12
[N/A]
U6
U5
[N/A]
fitted
fitted
SB38
CRE_CS2
VDD_VCORE
VDD_VCORE
SB39
1V8_LCD
PSRAM_VDD
SB38
SB39
0R
[N/A]
0R
[N/A]
1.8V CORE only
32M bits
16M bits
SB39 for U6 only