Hardware layout and configuration
UM2271
24/78
DocID030906 Rev 2
10.9 Boot
configuration
After reset, STM32L4R9AI boots from one of the three different embedded memory
locations, depending on BOOT0 and BOOT1 bits:
•
Boot from the main Flash memory (MCU internal Flash). This is the default
configuration.
•
Boot from the system memory ISP (in-system programming).
•
Boot from the SRAM1.
On 32L4R9IDISCOVERY board, the boot configuration of the MCU is controlled by the
BOOT0 signal on PH3 pin.
BOOT0 is by default grounded through the R15 pull-down resistor.
It is possible to set BOOT0 high by removing resistor R15 and populating resistor R16 with
a 10K resistor.
Please check below
for other boot modes.
10.10 Audio
codec
A Cirrus codec CS42L51-CNZ U26 connected to the SAI1 interface of STM32L4R9AI offers
possibility to connect a stereo headphone or headset with a mono analog microphone.
The I²C-bus addresses of CS42L51-CNZ are 0x95 and 0x94.
10.11 DFSDM
Two ST-MEMS MP34DT01TR digital microphones U1 and U2 are available on
32L4R9IDISCOVERY. The two microphones are located at a distance of 21 mm from each
other. They are connected to the STM32 DFSDM by the PC2 port, generating the clock, and
Table 10. Boot modes
nBOOT1
FLASH_OPTR[23]
nBOOT0
FLASH_OPTR[27]
BOOT0 pin
PH3
nSWBOOT0
FLASH_OPTR[26]
Boot Memory Space Alias
X
X
0
1
Main Flash memory is selected
as boot area
X
X
0
1
System memory is selected as
boot area
X
1
X
0
Main Flash memory is selected
as boot area
0
X
1
1
Embedded SRAM1 is selected
as boot area
0
0
X
0
Embedded SRAM1 is selected
as boot area
1
X
1
1
System memory is selected as
boot area
1
0
X
0
System memory is selected as
boot area
