Stanford Research Systems DS345, Руководство пользователя

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DS345 Circuitry
8-2
U306 also provides an output for the key-click speaker, S300. U303, U304,
and U305 provide output bits for all of the front panel LEDs.
RIBBON CABLE, TRIGGER, AND SYNC SELECT (SHEET 4 OF 7)
JP401 is the connector for the ribbon cable carrying all of the signals to and
from the top PC board. Every signal line is alternated with a ground or power
line to minimize crosstalk.
U401 is the trigger multiplexer, and selects the DDS trigger source. A trigger
error is indicated if U211B detects that the unit is already triggered or sweep-
ing when a trigger occurs.
U402 and U403 provide drive for the SYNC, TRIG, BLANK, and MARKER
outputs.
JP400 is the connector for the top board power supplies, with the exception
of the 5 volt logic supply, which is carried on JP401.
GPIB AND RS232 INTERFACES (SHEET 5 OF 7)
The field installable interface PCB offers RS232 and GPIB communications
that are optically isolated from the DS345's floating circuitry. All connections
are made via JP501.
The RS232 interface is handled by U512, which generates the required
RS232 levels from the 5-volt interface supply. The RS232 data in and out as
well as DTR signals are optically coupled directly to the Z8800 processor
UART during RS232 communication through U523, U520, and U522, respec-
tively.
During GPIB communications, the parallel GPIB data is handled by shifting
the data and control information in and out through shift registers U503 and
U504. Along with the data clock (through opto-coupler U521), the circuit
communicates through the Z8800 UART at 1x clock frequency, or 1.25
MBaud. U515B detects the serial start bit and forces an output queue start
bit through U518A. The SHIFT_CLK then begins after a one bit delay by
U518B. U506 generates eight clock cycles, after which the RCO output of
this counter resets the start bit detect flip-flop, disables the SHIFT_CLK, and
generates an output queue stop bit by presetting U518A.
The first incoming 8 data bits are shifted into U504, the command register, af-
ter which they are cascaded into U503,the data register. U503 transfers data
to and from the GPIB controller U500, and U504 sets the appropriate bits to
define the direction of data flow, etc.. U517A and RC delay R501/C501 gen-
erate a delayed clock to clock data in the reverse direction (parallel in) into
U503, along with mode bit S0 (from COMMAND STROBE). In other words,
when COM_STB goes high (setting S0 on U503 high), the delayed clock
from U517A latches the input data into U503 from the GPIB controller.