24
threshold, reference oscillator frequency,
display contrast, and to calibrate assorted
current sources. Each of the 30 D/A sample and
hold circuits is refreshed for 1ms every 30ms.
DIGITAL TO ANALOG CONVERTER
The 12-bit D/A converter is loaded by the Z-80
four bits at a time. The current output from the
D/A is converted to a voltage by 1/4 of U402
with a full-scale range of 0 to -10.24VDC. The
D/A voltage is offset and/or attenuated by 2/4,
3/4 and 4/4 of U402.
The output of 4/4 of U402, which controls the
amplitudes of all of the front panel outputs, is
referenced to the -6.0VDC power supply. This is
so that variations in the -6.0VDC supply will not
change the amplitude current source.
The output of 2/4 of U402, which controls the
current sources that calibrate the analog time
delay circuits, is referenced to the +15.0VDC
supply. This is done so that variations in the
+15.0VDC supply will not change the
calibration of the analog time delays.
TIMEBASE
The basic time interval for all the digital delays
is an 80MHz oscillator. The 80MHz is
generated by a varactor-tuned VCO which is
phase locked to a 10.000MHz reference. There
are three sources for the 10.000MHz reference:
a standard 10.000MHz reference with a 25ppm
maximum error over 0 to 50°C, an optional
10.000MHz reference with a 1ppm maximum
error, or a user supplied source. The optional
1ppm oscillator is powered from a doubly
reg12VDC source (U509) and is
varactor tuned by a D/A output to better than
1Hz accuracy. (See calibration procedure to set
the frequency.)
The internal reference is selected when the rear
panel switch is in the INT position. In this
position, the 10.000MHz source is shifted to
ECL levels by Q502 and Q503 and passed to the
ECL phase comparator U502, a MC12040 . The
output of the phase comparator is filtered by the
two-pole active low-pass filter (U503 and
passive components). The filter output is
buffered by Q504 and used to control the
frequency of the varactor-tuned LC-tank
oscillator. The window comparator, U507, is used to
detect gross frequency errors as might be expected if
an external reference has insufficient amplitude or a
frequency more than a few percent off the nominal
10.000MHz.
The 80MHz output serves as the basic unit of time
in all of the digital delays. The 80Mhz is divided by
8 to generate a 10MHz signal which is used to close
the phase-locked-loop. The 10MHz ECL signal is
shifted to TTL levels by 3/4 of U107, and buffered
by Q505, to provide a nominal 1Volt square wave
into 50
Ω
at the rear panel
1
0.000MHz BNC. The
10MHz TTL signal is also used as the clock to the
frequency synthesizer circuits.
FREQUENCY SYNTHESIZER
The "bottom" PCB provides a 10 MHz frequency
source to the "top" PCB, which is used as the
reference for all synthesized frequencies on the
"top" PCB. The 10MHz source is divided by two
(1/2 U101) to generate the 5MHz clock for the Z-80.
The 5MHz is in turn divided by 2 (2/2 U101) to
provide a 2.5MHz clock to 3/3 of U209 (a uPD8253
Counter/Timer) which is divided by 2500 to produce
a 1KHz clock to the timer interrupt flag, 1/2 U307 (a
74HC74).
U112 divides the 1KHz clock to generate a 100Hz
clock, which is the reference source for the internal
rate synthesizer. A CMOS VCO/PLL (U110) is
phase locked to an integer multiple (x1000 to
x10,000 per 1/3 U210) of the 100Hz reference. The
VCO output (100KHz to 1MHz) is then divided by
two more LSI counter/timer channels (2/3 and 3/3 of
U210)to generate any frequency between 0.001Hz
and 1.000MHz.
LINE TRIGGER
The 8 VAC tap on the power transformer is
discriminated by the comparator 1/4 of U502. This
line trigger is then synchronized to the 80 MHz
timebase by the flip-flop, 2/2 of U307, which is
clocked by the 2.5 MHz signal, which has been
divided down from the 80 MHz clock.
Synchronizing the trigger to the 80 MHz timebase
reduces the jitter of the delay outputs to about 25 ps
rms.
TRIGGER SELECTION
Three control bits are used to select the operating
mode of the internal rate generator. These bits are
