Standart HX290U, Руководство по обслуживанию

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2.1.6 VCO Circuit
The DC voltage output by the PLL loop filter is input to a
variable capacitance diode built into the VCO. This DC
voltage changes the capacitance between the electrodes
of the variable capacitance diode, thereby controlling the
oscillation signal of the VCO.
2.1.7 Unlock Detect Circuit
The microprocessor QL02 (pin 37) determines whether
the status of the PLL circuitry is lock or unlock according
to the output level (high or low) from pin 14 of the PLL IC.
If the phase comparator built into the PLL IC detects no
phase difference (PLL circuit locked), it produces a high
level output. This high level output signal is input to an
unlock switch QP04, causing it to turn on. When the
unlock switch is on, a low level output signal is input to pin
37 of microprocessor QL02. The low level input causes
microprocessor QL02 to determine that the PLL circuit is
locked.
If there is a phase difference (PLL circuit unlocked), the
phase comparator produces a low level output. This low
level output signal is input the unlock switch QP04,
causing it to turn off. When the unlock switch is off, a high
level output signal is input to pin 37 of microprocessor
QL02. The high level input causes microprocessor QL02
to determine that the PLL circuit is unlocked.
2.2 Receiver Block
The reception method is double-conversion superheterodyne with a first IF frequency of 44.95 MHz (Lower) and a second IF
frequency of 455 kHz (Lower). The receiver block comprises an RF amplifier circuit, first mixer circuit, first IF amplifier circuit,
second IF circuit, and audio circuit.
QH04
TA31136FN
Antenna switch
RF amplifier
First IF amplifier
Second IF IC
Crystal filter First mixer
QT04-HVU131
QT05-HSC277
16
B.P.F.
QF02
2SK274
QF03
SGM2014AM
FH01
First local signal (Approx. 300 mV)
(20 dB amp)
(20 dB amp)
L.P.F.
B.P.F.
QH03-2SC4649
Audio signal
Figure 2-2 Receiver block diagram
2.2.1 RF Amplifier Circuit
The reception frequency amplified by approximately 20 dB
by RF amplifier QF02, after which it is input to a band-pass
filter consisting of LF04, CF11, CF29, CF13, LF05, CF14,
CF15, LF06, CF16, CF17, CF18, LF07, CF19(only
HX290UKA131/181/111) and CF20. At this point, unwanted
frequency elements removed by the band-pass filter.
2.2.2 First Mixer Circuit
The reception frequency (fr
X
) is mixed with the first local
signal (fvco) from the VCO by first mixer QF03, and first
IF signals consisting of their difference are generated.
frx - fvco = 44.95 (MHz)
frx : Reception frequency
fvco : First local signal
2.2.3 First IF Amplifier Circuit
Bandwidth of crystal filter FH01 depends on setting of
channel separation.
After being amplified by approximately 20 dB by first IF
amplifier QH03, the 44.95 MHz first IF signal is input to
pin 16 of second IF IC QH04.