Development and debugging tool support
AN2339
12/20
5
Development and debugging tool support
The STR91xF device supports connection to both In-Circuit Emulators (ICE) via standard
JTAG interface and trace tools via an Embedded Trace Macrocell (ETM9) interface.
5.1 JTAG
interface
The STR91x has a user debug interface. It contains a six-pin serial interface conforming to
JTAG, IEEE standard 1149.1-1993, “Standard Test Access Port-Scan Boundary
Architecture”. JTAG allows the ICE device to be plugged to the board and used to debug the
software running on the STR91x.
JTAG emulation allows the core to be started and stopped under control of the connected
debugger software. The user can then display and modify registers and memory contents,
and set break and watch points.
5.1.1
JTAG interface pins
The JTAG interface pins consist of the following signals:
Table 1.
JTAG interface signals
Std name
STR91x
name
Direction/
Description
Function
nTRST
JTRST
Test Reset (from
JTAG equipment)
This active LOW open-collector is used to reset
the JTAG port and the associated debug
circuitry. It is asserted at power-up by each
module, and can be driven by the JTAG
equipment.
TDI
JTDI
Test data in (from
JTAG equipment)
TDI goes down the stack of modules to the
motherboard and then back up the stack,
labelled TDO, connecting to each component
in the scan chain.
TMS
JTMS
Test mode select
(from JTAG
equipment)
TMS controls transitions in the tap controller
state machine. TMS connects to all JTAG
components in the scan chain as the signal
flows down the module stack.
TCK
JTCK
Test clock (from
JTAG equipment)
TCK synchronizes all JTAG transactions. TCK
connects to all JTAG components in the scan
chain. Series termination resistors are used to
reduce reflections and maintain good signal
integrity. TCK flows down the stack of modules
and connects to each JTAG component.
However, if there is a device in the scan chain
that synchronizes TCK to some other clock,
then all down-stream devices are connected to
the RTCK signal on that component.