When the Backup domain is supplied by V
DD
(analog switch connected to the VDD pin), the following pins are
available:
•
PC13, PC14 and PC15, that can be used as GPIO pins
•
PC13, PC14 and PC15, that can be configured by RTC or LSE (refer to the RTC section of the reference
manual)
•
Pins listed below, that are configured by TAMP as tamper pins:
–
PE3 (TAMP_IN6/TAMP_OUT3)
–
PE4 (TAMP_IN7/TAMP_OUT8)
–
PE5 (TAMP_IN8/TAMP_OUT7)
–
PE6 (TAMP_IN3/TAMP_OUT6)
–
PC13 (TAMP_IN1/TAMP_OUT2)
–
PA0 (TAMP_IN2/TAMP_OUT1)
–
PA1 (TAMP_IN5/TAMP_OUT4)
–
PC5 (TAMP_IN4/TAMP_OUT5)
Note:
•
Due to the fact that the power switch can transfer only a limited amount of current (3 mA), the use of
PC13 to PC15 I/Os in output mode is restricted: the speed must be limited to 2 MHz with a maximum load
of 30 pF. These I/Os must not be used as current source (for example to drive a LED).
•
Under V
DD
, TAMP_OUTx pins (PE3, PE4, PE5, PE6, PA0, PA1, PC5) keep the same speed features as
the GPIOs to which they are connected. However, under V
BAT
, the speed of TAMP_OUTx pins must be
limited to 500 kHz.
•
The speed of PC13 pin is always limited to 2 MHz, under V
DD
or under V
BAT
.
Backup domain access
After a system reset, the Backup domain (RCC_BDCR, PWR_BDCR1, RTC, TAMP and backup registers, plus
backup SRAM) is protected against possible unwanted write accesses. To enable access to the Backup domain,
proceed as follows:
1.
Enable the power interface clock by setting the PWREN bit in RCC_AHB3ENR register.
2.
Set the DBP bit in PWR_DBPR register to enable access to the Backup domain.
V
BAT
battery charging
When V
DD
is present, the external battery can be charged on V
BAT
through an internal resistance, 5 kΩ or 1.5 kΩ,
depending on the VBRS bit in PWR_BDCR2 register.
The battery charging is enabled by setting VBE bit in PWR_BDCR2. It is automatically disabled in VBAT mode.
2.1.5
Voltage regulator
The STM32U575/585 devices embed the following internal regulators in parallel to provide the V
CORE
supply for
digital peripherals, SRAM1/2/3/4, and embedded Flash memory:
•
SMPS step-down converter
•
LDO (linear voltage regulator)
They can be selected when the application runs, depending on the application requirements. The SMPS allows
the power consumption to be reduced, but the noise generated by the SMPS may impact some peripheral
behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best
performances.
Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges
(range 1/2/3/4), in all Stop modes (Stop 0/1/2/3) and in Standby with SRAM2 (refer to the 'low-power mode
summary' table in the reference manual).
The STM32U575/585 devices without SMPS embed only the LDO regulator, that controls all voltage-scaling
ranges and power modes.
AN5373
Power supplies
AN5373
-
Rev 1
page 7/37
