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6

Debug management

The serial wire/JTAG debug port (SWJ-DP) is an Arm standard CoreSight

™

 debug port.

The host/target interface is the hardware equipment that connects the host to the application board. This interface
is made of three components: a hardware debug tool, a serial-wire connector and a cable connecting the host to
the debug tool.
The figure below shows the connection of the host to a development board.

Figure 8. 

Host-to-board connection

STM32 board

Host

PC

Power supply

JTAG/serial-wire connector

Debug tool

The Nucleo demonstration board embeds the debug tools (ST-LINK), so it can be directly connected to the PC
through an USB cable.

6.1

SWJ-DP (serial-wire and JTAG debug port)

The SWJ-DP combines:
•

a JTAG

‑

DP that provides a 5-pin standard JTAG interface to the AHP-AP port

•

a SW-DP that provides a 2-pin (clock + data) interface to the AHP-AP port

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.

Note:

All SWJ-DP port I/Os can be reconfigured to other functions by software, but debugging is no longer possible.

6.2

Pinout and debug port pins

The devices are offered in various packages with different numbers of available pins. As a result, some
functionality related to the pin availability may differ from one package to another.

6.2.1

SWJ-DP pins

Five pins are used as outputs for the SWJ-DP, as alternate functions of the GPIOs (general-purpose I/Os). These
pins, detailed in the table below, are available on all packages.

Table 6. 

Debug port pin assignment

SWJ-DP pin

JTAG debug port

SW debug port

Pin assignment

Type

Description

Type

Debug assignment

JTMS/SWDIO

Input

JTAG test mode selection Input/Output Serial

‑

wire data input/output

PA13

JTCK/SWCLK

Input

JTAG test clock

Input

Serial

‑

wire clock

PA14

JTDI

Input

JTAG test data input

-

-

PA15

JTDO/TRACESWO Output JTAG test data output

-

TRACESWO if asynchronous trace
is enabled

PB3

JNTRST

Input

JTAG test nReset

-

-

PB4

AN5373

Debug management

AN5373

 - 

Rev 1

page 22/37

Содержание STM32U575 Series

Страница 1: ...5xx and STM32U585xx microcontrollers also named STM32U575 585 and describes the minimum hardware resources required to develop an application using these MCUs Detailed reference design schematics are...

Страница 2: ...on This document applies to the STM32U575 585 Arm based microcontrollers Note Arm is a registered trademark of Arm Limited or its subsidiaries in the US and or elsewhere AN5373 General information AN5...

Страница 3: ...LDO only no SMPS connected to a total of 4 7 F typical external capacitor Note In case there is two VCAP pins UFBGA169 package each pin must be connected to a 2 2 F capacitor for a total around 4 4 F...

Страница 4: ...ackage the internal VREFBUF is not available and must be kept disabled VREF must always be equal to VSSA The following figures present an overview of the STM32U575 585 devices power supply depending o...

Страница 5: ...lows VDDSMPS and VLXSMPS connected to VSS VDD11 pins connected to VSS through two 2 2 F capacitors as in normal mode 2 1 1 Independent analog peripherals supply To improve ADC and DAC conversion accur...

Страница 6: ...VDD or VDDA After reset the USB features supplied by VDDUSB are logically and electrically isolated and are therefore not available The isolation must be removed before using the USB OTG peripheral b...

Страница 7: ...to the Backup domain proceed as follows 1 Enable the power interface clock by setting the PWREN bit in RCC_AHB3ENR register 2 Set the DBP bit in PWR_DBPR register to enable access to the Backup domain...

Страница 8: ...ssible select VDDA or VDDA booster rather than VDD as they are often less noisy The analog switches for TSC function are supplied by VDD 2 2 Power supply schemes The device is powered by a stabilized...

Страница 9: ...elow details the power supply schemes for packages with and without SMPS Figure 3 Power supply scheme for STM32U575x and STM32U585x without SMPS VDDIO2 VDD Level shifter I O logic Kernel logic CPU dig...

Страница 10: ...H 2 x 2 2 F 10 F SMPS ON SMPS OFF LDO SMPS VDDUSB 3 3 V 100 nF Voltage regulator Note SMPS and LDO regulators provide in a concurrent way the VCORE supply depending on application requirements Howeve...

Страница 11: ...emain below VDD 300 mV When VDD is above 1 V all power supplies are independent Figure 5 Power up power down sequence 0 3 1 VDD_MIN VDD_MAX Operating mode Power on Power down time V VDDX 1 VDD Invalid...

Страница 12: ...d When VDD is above the VBORx upper limit the device reset is released and the system can start For more details on the Brownout reset thresholds refer to the electrical characteristics section in the...

Страница 13: ...reset circuit External reset VDD RPU WWDG reset Software reset Low power manager reset IWDG reset Option byte loader reset Pulse generator min 20 s NRST System reset Filter BOR 2 4 3 Backup domain re...

Страница 14: ...mission or signal integrity of high speed interfaces Smaller packages usually provide better signal integrity This is further enhanced as small pitch and high ball density requires multilayer PCBs tha...

Страница 15: ...X X X X X X X PH3 BOOT0 X X X X X X X X X X X X X Power pins VBAT X X X X X X X X X X X X X VDDUSB 2 X X X X X X X X X X X VSSA 3 o o X o X o o o o o o o o VREF o o X o X o o o o o o o o VREF 4 o o X...

Страница 16: ...power supply pins of the above table Example VDDIO2 is the pin number 130 on SMPS package Pin 130 on the package without SMPS is mapped to a VSS pin It means the system is short circuited when a lega...

Страница 17: ...time clock rtc_ck HSI48 internal 48 MHz RC that potentially drives the OTG FS the SDMMC and the RNG SHSI secure high speed internal RC that drives the secure AES SAES PLL2 and PLL3 clocks Each clock s...

Страница 18: ...the square signal is recommended 4 2 HSI16 clock The HSI16 clock signal is generated from an internal 16 MHz RC oscillator The HSI16 RC oscillator provides a clock source at low cost no external compo...

Страница 19: ...s itself thanks to the LSE This mode is available for all MSI frequency ranges At 48 MHz the MSIK in PLL mode can be used for the USB OTG FS device avoiding the need of an external high speed crystal...

Страница 20: ...R 27 BOOT0 pin PH3 nSWBOOT0 FLASH_ OPTR 26 Boot address option byte selection Boot area ST programmed default value 0 1 NSBOOTADD0 24 0 Boot address defined by user option bytes NSBOOTADD0 24 0 Flash...

Страница 21: ...1 on pins PA9 PA10 USART2 on pins PA2 PA3 USART3 on pins PC10 PC11 I2C I2C1 on pins PB6 PB7 I2C2 on pins PB10 PB11 I2C3 on pins PC0 PC1 SPI SPI1 on pins PA4 PA5 PA6 PA7 SPI2 on pins PB12 PB13 PB14 PB1...

Страница 22: ...the SW DP are multiplexed with some of the five JTAG pins of the JTAG DP Note All SWJ DP port I Os can be reconfigured to other functions by software but debugging is no longer possible 6 2 Pinout an...

Страница 23: ...control the debug mode features Special care must be taken with the SWCLK TCK pin that is directly connected to the clock of some of these flip flops To avoid any uncontrolled I O levels the devices e...

Страница 24: ...WCLK Input Serial wire clock PA14 After reset the pins used for the SWD are assigned as dedicated pins that can be immediately used by the debugger host However the MCU offers the possibility to disab...

Страница 25: ...elow shows the connection between the device and a standard SWD connector Figure 10 SWD connector implementation CN1 NRST SWCLK PA14 SWDIO PA13 SWD connector VDD 10 9 8 7 6 5 4 3 2 1 STM32U5 device AN...

Страница 26: ...power supplies VSS VDD VSSA VDDA VDDUSB VDDIO2 or VDDSMPS must be implemented close to the ground line to minimize the area of the supplies loop This is due to the fact that the supply loop acts as a...

Страница 27: ...gin must be reached for the two logical states Slow Schmitt triggers are recommended to eliminate parasitic states Noisy signals example clock Sensitive signals example high impedance 7 6 Unused I Os...

Страница 28: ...n figures shown in Section 8 2 The reset sources include the reset button B1 debugging tools via the connector CN1 Refer to Section 2 4 for more details Boot mode The user can add a switch on the boar...

Страница 29: ...17 C21 Ceramic capacitor 100 nF 17 For each external power pin C18 C19 Tantalum or ceramic capacitor 2 2 F 2 Required on each VDD11 pin of packages with SMPS C8 C11 4 7 F C8 as decoupling capacitor C1...

Страница 30: ...Figure 12 STM32U575xxx reference design without SMPS AN5373 Component references AN5373 Rev 1 page 30 37...

Страница 31: ...Figure 13 STM32U575xxQ reference design with SMPS AN5373 Component references AN5373 Rev 1 page 31 37...

Страница 32: ...Revision history Table 10 Document revision history Date Version Changes 21 Jun 2021 1 Initial release AN5373 AN5373 Rev 1 page 32 37...

Страница 33: ...and VDD 11 2 3 1 Power supply isolation 11 2 3 2 General requirements 11 2 3 3 Particular conditions during power down phase 11 2 4 Reset and power supply supervisor 12 2 4 1 Brownout reset BOR 12 2...

Страница 34: ...4 6 3 Serial wire debug SWD pin assignment 24 6 3 1 Internal pull up and pull down on SWD pins 24 6 3 2 SWD port connection with standard SWD connector 25 7 Recommendations 26 7 1 PCB printed circuit...

Страница 35: ...4 Boot modes when TrustZone is disabled TZEN 0 20 Table 5 Boot modes when TrustZone is enabled TZEN 1 21 Table 6 Debug port pin assignment 22 Table 7 SWJ DP I O pin availability 23 Table 8 SWD port pi...

Страница 36: ...STM32U585xQ with SMPS 10 Figure 5 Power up power down sequence 11 Figure 6 Brownout reset waveform 12 Figure 7 Simplified diagram of the reset circuit 13 Figure 8 Host to board connection 22 Figure 9...

Страница 37: ...ts and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST pro...

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