Figure 9.
JTAG, Nexus and SIPI
Place CAPS as close to
connector pins as
possible but do NOT fit
caps at board assembly.
JTAG Connector
(VSS)
(VSS)
(VSS)
(VSS)
JTAG interface
SIPI interface
DRCLK
Nexus interface
RDY not implemented on SPC57xxmM
TDI, TDO, TCK, TMS & JCOMP are not connected to
daughter card.
PORST, ESR0, EVTI and EVTO are connected to daughtercard
LVDS signals are not routed to motherboard.
JTAG signals are not routed to motherboard.
EVT signals have the option of adding a jumper on
daughtercard to route signals to motherboard.
Previson Eiger DC-DC Regulator
ball E14
(smps_pmos0)
ball D15
(smps_vlx)
ball D14
(smps_nmos1)
EVTI
TDO
ESR0
TCK
TMS
TDI
JCOMP
TMS
JCOMP
PF14
SIPI_TXP
SIPI_TXN
TX0P
TX0N
TX1P
TX1N
TX2P
TX2N
TX3P
TX3N
TCK
TMS
TDI
TDO
JCOMP
EVTI1
EVTI0
EVTO0
PORST
ESR0
EVTO1
PORST
PORST
SIPI_RXN
SIPI_RXP
EVTO
PH0
PG15
PH1
VDD_HV_IO_JTAG
GND
GND
GND
GND
GND
3.3V_SR
GND
VDD_HV_IO_JTAG
VDD_HV_IO_MAIN
GND
GND
TDI
(pg4,6)
TDO
(pg4,6)
TCK
(pg4,6)
)
4
g
p
(
I
T
V
E
JCOMP
(pg4,6)
TMS
(pg4,6)
SIPI_TXP
(pg4)
SIPI_TXN
(pg4)
SIPI_RXN
(pg4)
SIPI_RXP
(pg4)
TX0P
(pg4)
TX0N
(pg4)
TX1P
(pg4)
TX1N
(pg4)
TX2P
(pg4)
TX2N
(pg4)
TX3P
(pg4)
TX3N
(pg4)
PF14 (pg4,5)
TCK (pg4,6)
TMS(pg4,6)
TDI (pg4,6)
TDO (pg4,6)
JCOMP (pg4,6)
EVTI1 (pg4)
EVTI0 (pg4)
EVTO0 (pg4)
PORST(pg4,6,7)
ESR0
(pg4,6,7)
CLKP (pg4)
CLKN (pg4)
EVTO1 (pg4)
ESR0
(pg4,6,7)
PORST
(pg4,6,7)
EVTO
(pg4)
SMPS_REGULATOR_OUT
PH[0..15]
(pg4)
PG[0..15]
(pg4)
J37
STRIP
2
1
3
4
5
6
J20
ERF8-005-05.0-L-DV-L-TR
1
2
3
4
6
5
7
8
9
10
11
12
J18
N2514-6002RB
1
2
3
4
6
5
7
8
9
10
11
12
13
14
J19
SAMTEC ASP-137973-01
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
19
23
29
25
17
27
21
31
32
33
34
SH1
SH2
C117
100pF
R3
10K
DNP
R22
0R
C119
100pF
C57
47pF
DNP
C56
47pF
DNP
R4
10K
R23
0R
R20
0R
R24
0R
C120
27pF
J36
STRIP
2
1
3
4
5
6
R21
0R
UM2764
-
Rev 1
page 20/26
UM2764
Schematics
