ST SPC563M64CAL144, Справочное руководство

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Calibration bus interface and External Memory RM0345
12/38 Doc ID 024080 Rev 3
4 Calibration bus interface and External Memory
The SPC563M64xx features a 16-bit de-multiplexed calibration bus interface that is
connected to an external 2Mbyte SRAM thanks to an on board latch.
4.1 External memory specification
The calibration board provides a SRAM with the following characteristics:
– 2Mbyte static RAMs organized as 1024K words by 16 bits;
– 16-bit data width;
– Fully static operation: no clock or refresh required;
– 3.3V input supply;
– /CE power-down;
– High-speed access time (10ns);
– Full automotive temperature range;
– Lead-free.
When /CE is HIGH (deselected), the device assumes a standby mode at which the power
dissipation can be reduced down with CMOS input levels.
4.2 SRAM supply and data retention function
The circuitry in Figure 6 has been implemented on the calibration board to protect the
memory and to guarantee that the Working Page is valid after a power fail of the target
application by putting the SRAM in standby powered.
The 3.3 V supply of the SRAM (Vmem) is gated by the RESET and RSTOUT signals of the
SPC563M64xx.
The memory enable is driven via the SPC563M64xx chip select C_CS0 “and” the RESETs
signals combination.