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RM0345

Reset and configuration signals

Doc ID 024080 Rev 3

11/38

3 

Reset and configuration signals

Calibration and debug tools may use the reset signals included in the    connectors to have 
visibility of when the SPC563M64xx device has been reset. Debug tools may also require 
the ability to force device reset.

All signals of the SPC563M64xx QFP144 footprint from the application board are directly 
connected to the respective calibration device signals. This includes the following signals on 
the 

Table 3

.

         

Table 3.

Reset and configuration signals

Signal name

Function

Notes

Reset / Configuration (5)

/RESET

External reset input

The /RESET pin is an active low input. The 
RESET pin is asserted by an external device 
during a power-on or external reset. The 
internal reset signal asserts only if the RESET 
pin asserts for 10 clock cycles. Assertion of 
the RESET pin while the device is in reset 
causes the reset cycle to start over.

/RSTOUT

External reset output

The RSTOUT pin is an active low output that 
uses a push/pull configuration. The RSTOUT 
pin is driven to the low state by the MCU for all 
internal and external reset sources. There is a 
delay between initiation of the reset and the 
assertion of the RSTOUT pin.

BOOTCFG[1]

Boot configuration input

The BOOTCFG field holds the value of the 
BOOTCFG[1] pin that was latched on the last 
negation of the RSTOUT pin. The BOOTCFG 
field is used by the BAM program to 
determine the location of the Reset 
Configuration Word.

PLLREF

FMPLL Mode Selection

PLLREF is used to select whether the 
oscillator operates in xtal mode or external 
reference mode from reset.

If RSTCFG is 0, External reference clock 
selected.

If RSTCFG is 1, Xtal oscillator mode is 
selected

WKPCFG

Weak Pull Configuration

The signal on the WKPCFG pin determines 
whether weak pull up or pull down devices are 
enabled after reset on the eTPU and eMIOS 
pins.

0: Weak pulldown applied to eTPU and 
eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS 
pins at reset.

Содержание SPC563M64CAL144

Страница 1: ...e microcontrollers The SPC563M64CAL144 rev B can be fitted onto the application printed circuit board PCB in place of the standard SPC563M64xx family microcontroller in LQFP144 package SPC563M64CAL144...

Страница 2: ...nction 12 4 3 Calibration bus interface 14 5 Development connector 15 6 Calibration connector 17 7 Tool IO 19 8 CAN interface 20 9 Calibration software compatibility and configuration 22 9 1 Calibrati...

Страница 3: ...RM0345 Contents Doc ID 024080 Rev 3 3 38 Revision history 37...

Страница 4: ...us signals on AMP 38 Mictor connector 16 Table 7 Nexus signals on AMP 38 Mictor connector 17 Table 8 J12 J13 FlexCAN interface selection 20 Table 9 J6 J17 and J7 FlexCAN interface selection 21 Table 1...

Страница 5: ...iagram 14 Figure 8 JP1 development connector 15 Figure 9 AMP 38 Mictor 16 Figure 10 J9 Calibration connector 17 Figure 11 Calibration triggers TOOL_IO 19 Figure 12 CAN schematic diagram 20 Figure 13 T...

Страница 6: ...de these distinctive features Use 100 production silicon ensuring full hardware and software compatibility between production and calibration systems Support LQFP144 MCU production package allowing ca...

Страница 7: ...when the board is powered Figure 2 Power supply By default the 5V is taken from the target application through the VDDREG supply level supply input for the internal voltage regulators of the SPC563M6...

Страница 8: ...he VDDE12 supply used to power the dedicated SPC563M64xx calibration bus interface is connected to the upon board 3 3 V voltage regulator VSSAVSSSYN GND VRCCTL VDDREG VSTBY C46 1uF GND VDDEH1 A 24 VDD...

Страница 9: ...gauge In this case the gauge J15 must be open Table 2 B5 B 5 B B B2 B76 B0 2 B 972 9 9 95 YUFSOBM VT OUFSGBDF B 0 B 0 B 9 B B 7 B B B 8 B 9 B B B 7 B 7 B 7 9 B 7 B 7 8 B 7 8 B 7 7 B 7 7 B 7 B 7 B 7 B...

Страница 10: ...signal is disconnected from the target application board close default VRC33 signal is connected to the target application board J2 VRC33 open default VRC33 signal is disconnected from the on board 3...

Страница 11: ...causes the reset cycle to start over RSTOUT External reset output The RSTOUT pin is an active low output that uses a push pull configuration The RSTOUT pin is driven to the low state by the MCU for al...

Страница 12: ...d 3 3V input supply CE power down High speed access time 10ns Full automotive temperature range Lead free When CE is HIGH deselected the device assumes a standby mode at which the power dissipation ca...

Страница 13: ...ation connector J9 see Figure 10 Table 4 J11 configuration of SRAM supply for retention mode J11 SRAM standby supply source all open ECU_Stby standby voltage on J9 calibration connector 1 2 closed Upo...

Страница 14: ...ctionality of this signal indicates to the external latch when to capture the address signals Figure 7 SRAM schematic diagram The Section 9 Calibration software compatibility and configuration shows t...

Страница 15: ...cut trace J3 J5 and J10 are listed on Figure 5 Table 5 J3 J5 and J10 option cut traces option name Function Value Note J3 CLKOUT open CLKOUT signal is disconnected to the Nexus JP1 connector close def...

Страница 16: ...ut trace option Table 6 Nexus signals on AMP 38 Mictor connector Pin Description Pin Descriptio 1 nc 2 nc 3 nc 4 nc 5 C_MDO9 6 CLKOUT 7 BOOTCFG1 8 C_MDO8 9 RESET 10 C_EVTI 11 TDO 12 3 3V 13 C_MDO10 14...

Страница 17: ...tandard function Pin SPC563M64xx routing standard function B1 nc nc A1 nc nc B2 nc nc A2 JCOMP JTAG interface B3 RSOUT RSOUT A3 CAL Wakeup 12V output for Wakeup functionality B4 GND GND A4 C_EVTI JTAG...

Страница 18: ...g A12 MDO 0 Detect that the PLL is locked B13 ECU_Vsby VDDSBRAM Supply Backup Voltage of ECU Standby RAM A13 5V VDDP Comparator Input Supply of microcontroller Interface Pins Table 7 Nexus signals on...

Страница 19: ...kes On the calibration board these signals are available on the JP1 development connector and J9 calibration connector By default GPIO 206 GPIO 207 are powered by VDDEH at 5V A level shifter see Figur...

Страница 20: ...transceiver in high speed and fault tolerant networks from ESD and other harmful transient voltage events see Figure 12 The L9616 CAN transceiver has an Adjustable Slope Control ASC feature that sets...

Страница 21: ...t 3 3 V Note Refer to Section Appendix D Options placement for layout options placement Table 9 J6 J17 and J7 FlexCAN interface selection J6 or J17 if 3 3V J7 FlexCAN interface closed open low speed o...

Страница 22: ...s will output the address signals during the address phase by using an onboard external latch controlled by the CAL_TS signal The CAL_ALE may be used to drive an external latch when an asynchronous me...

Страница 23: ...is SIU_PCR suffixed by the PCR number 9 1 2 Cal Bus ECCR Settings The SIU ECCR registers used to control the timing relationship between the system clock and the external clock CLKOUT The external bus...

Страница 24: ...n the Table 14 Table 13 EBI_MCR register setting bit field Name Description value 29 D16_31 Data Bus 16_31 Select The D16_31 bit controls whether the EBI uses the DATA 0 15 or DATA 16 31 signals when...

Страница 25: ...hosen 20 PS Port Size The PS bit determines the data bus width of transactions to this chip select bank Note In the case where the DBM bit in EBI_MCR is set for 16 bit Data Bus Mode the PS bit value i...

Страница 26: ...order in the field allowing a resource to reside in more than one area of the address map This field can be read or written at any time 24 27 SCY Cycle length in clocks This field represents the numb...

Страница 27: ...DSC 20pF 0b01 SIU PCR 342 R 0x0040 CAL_RD WR CAL_WE 0 1 CAL_OE DSC 20pF 0b01 SIU PCR 343 R 0x0040 CAL_ALE DSC 20pF 0b01 SIU ECCR External Clock Control Register setup SIU ECCR R 0x1000 External Bus D...

Страница 28: ...Calibration software compatibility and configuration RM0345 28 38 Doc ID 024080 Rev 3 EBI Option Register setup Address mask 0xefe00000 Wait state 0 set 0 wait states EBI CAL_CS 0 OR R 0xffe00000...

Страница 29: ...an be fitted to an application PCB that has been designed to accept standard QFP144 packaged SPC563M64xx devices Bases can be supplied with solder footprints to allow direct and permanent soldered con...

Страница 30: ...Mechanical constrains RM0345 30 38 Doc ID 024080 Rev 3 Appendix B Mechanical constrains Figure 14 Top and side view drawing 3 5 6OJUT NN...

Страница 31: ...RM0345 Mechanical constrains Doc ID 024080 Rev 3 31 38 Figure 15 Side and bottom view drawing 3LQ 8QLWV PP 3 5...

Страница 32: ...Mechanical constrains RM0345 32 38 Doc ID 024080 Rev 3 Figure 16 Complete system side view drawing 3 5 8QLWV PP...

Страница 33: ...LKOUT AF25 VSS A2 VSS AD5 VSS AF26 VSS AF3 VSS AG1 VSS AG2 VSS AG27 VSS AG28 VSS AH1 VSS AH2 VSS AH27 VSS AH28 VSS B1 VSS B2 VSS B27 VSS B28 VSS C26 VSS C3 VSS E24 VSS E5 VSS G22 VSS G7 VSS H21 VSS H8...

Страница 34: ...ETPUA31 14 RSTOUT 85 RESET 80 WKPCFG 71 BOOTCFG1 70 PLLREF 68 Vss 36 Vss 59 Vss 73 Vss 22 Vss 115 Vss 91 Vss 104 Vss 48 VDD 26 VDD 53 VDD 86 VDD 120 EMIOS0 54 EMIOS2 55 EMIOS4 56 EMIOS8 57 EMIOS9 58...

Страница 35: ...GND GPIO207_3 3V GPIO206_3 3V 3 3V VSTBY 3 3V C31 1uF GND GND GND J7 5V 5V C44 100n C43 2 2uF CAN_HIGH CAN_LOW DEFAULT CLOSE DEFAULT OPEN J6 CNTX CNRX CNRX_C CNRX_A CNTX_A CNTX_C R2 60 R10 60 C45 100...

Страница 36: ...Options placement RM0345 36 38 Doc ID 024080 Rev 3 Appendix D Options placement Figure 20 Options placement TOP view Bottom view GAPGRI00358...

Страница 37: ...ision history Doc ID 024080 Rev 3 37 38 Revision history Table 16 Document revision history Date Revision Changes 18 Jan 2013 1 Initial release 13 Feb 2013 2 Modified Figure 14 17 Sep 2013 3 Updated D...

Страница 38: ...OPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PROD...

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