STA382BW
Register description: New Map
Doc ID 022783 Rev 1
To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any
audio streams flowing into the STA382BW data path before the desynchronization event
happens. At the same time any processing related to the I
2
C configuration should be issued
only after the serial audio interface and the internal PLL are synchronous again.
Note:
Any mute or volume change causes some delay in the completion of the I
2
C operation due
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
6.14.3
Delay serial clock enable
6.14.4
Channel input mapping
Each channel received via I
2
S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
2
S input channel to its corresponding processing channel.
6.15
Configuration register C (addr 0x13)
6.15.1
FFX compensating pulse size register
Table 35.
Delay serial clock enable
Bit
R/W
RST
Name
Description
5
R/W
0
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
2
S master devices
Table 36.
Channel input mapping
Bit
R/W
RST
Name
Description
6
R/W
0
C1IM
0: Processing channel 1 receives left I
2
S input
1: Processing channel 1 receives right I
2
S input
7
R/W
1
C2IM
0: Processing channel 2 receives left I
2
S input
1: Processing channel 2 receives right I
2
S input
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
CSZ3
CSZ2
CSZ1
CSZ0
Reserved
Reserved
1
0
0
1
0
1
1
1
Table 37.
FFX compensating pulse size bits
Bit
R/W
RST
Name
Description
2
R/W
1
CSZ0
When OM[1,0] = 11, this register determines the
size of the FFX compensating pulse from 0 clock
ticks to 15 clock periods.
3
R/W
1
CSZ1
4
R/W
1
CSZ2
5
R/W
0
CSZ3
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