ST QFN20, Руководство пользователя, Страница: 18 / 35

Introduction STCF03
18/35
The register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
7.10 Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF03 supports writing to multiple registers with
incremental addressing. When the data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See
Figure 10 below.
7.11 Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF03. The 8
th
bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of
the a R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF03 confirms the receiving of the a R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See
Figure 11
Figure 10. Writing to multiple register with incremental addressing
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K A
C
K S
T
O
P M
S
B
M
S
B
L
S
B L
S
B
DATA i+1
A
C
K L
S
B
DATA i+2
A
C
K L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K L
S
B
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K A
C
K S
T
O
P M
S
B
M
S
B
L
S
B L
S
B
DATA i+1
A
C
K L
S
B
DATA i+2
A
C
K L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K L
S
B S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K A
C
K S
T
O
P M
S
B
M
S
B
L
S
B L
S
B
DATA i+1
A
C
K L
S
B
DATA i+2
A
C
K L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K L
S
B
SDA LINE