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PulseBlasterESR  QuadCore 250 (Turbo)

 IV. Available Options

A number of off-the-shelf and custom options are available for this product.

1.Oven Controlled Clock Oscillator, when sub-ppm stability is required.
2.Higher clock frequency (custom design).
3.Additional TTL output bits per core (custom design).

     Please contact SpinCore Technologies, Inc. for more information, questions, or suggestions.   We look 

forward to hearing from you and helping you in your projects.   Please find our contact information below.

 V. Contact Information

SpinCore Technologies, Inc.

4623 NW 53rd Avenue, Suite 5

Gainesville, Florida 32653, USA

Phone:  +1-352-271-7383

Fax: 

+1-352-371-8679

Website:  

http://www.spincore.com

 

www.spincore.com

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02/17/09

Содержание PulseBlasterESR QuadCore 250 Turbo

Страница 1: ...PulseBlasterESR QuadCore 250 Turbo Owner s Manual SpinCore Technologies Inc http www spincore com ...

Страница 2: ... Technologies Inc reserves the right to make changes to the product s or information herein without notice PulseBlaster QuadCore PulseBlaster SpinCore and the SpinCore Technologies Inc logos are trademarks of SpinCore Technologies Inc All other trademarks are the property of their respective owners SpinCore Technologies Inc makes every effort to verify the correct operation of the equipment This e...

Страница 3: ...ct Overview 4 Programming Paradigm 4 II Installing and Using Your PulseBlasterESR QuadCore Board 5 Installation 5 General API Programming Information 5 III Test Programs 6 IV Available Options 7 V Contact Information 7 VI Document Information Page 8 www spincore com 3 02 17 09 ...

Страница 4: ...terval length is 229 clock cycles 2 15 seconds Each core has 1k 1024 memory words available for writing pulse programs i e there can be up to 1024 lines in your pulse program per core The basic architecture of the individual PulseBlaster processor cores is described in multiple documents including the Manuals for PulseBlaster and PulseBlasterESR boards available on line at the SpinCore s website w...

Страница 5: ...gned int core_sel function where the lower four bits of core_sel are used to select the cores bit0 corresponds to Core0 bit1 corresponds to Core1 etc and multiple combinations are acceptable i e a value of 0xF or 15 will select all four cores The overall system timing is based on Core0 in order to ensure that all cores are precisely synchronized This requires that Core0 be the last core or part of...

Страница 6: ...tput should be one 20 ns pulse on each BNC output connector and all four pulses should appear simultaneously on all four channels NOTE When attaching an oscilloscope to the board to observe the pulses care should be taken to use cables of the same type and length for each channel as skew can be induced due to propagation delays Conversely any inherent variations in on chip propagation delays can b...

Страница 7: ...itional TTL output bits per core custom design Please contact SpinCore Technologies Inc for more information questions or suggestions We look forward to hearing from you and helping you in your projects Please find our contact information below V Contact Information SpinCore Technologies Inc 4623 NW 53rd Avenue Suite 5 Gainesville Florida 32653 USA Phone 1 352 271 7383 Fax 1 352 371 8679 Website h...

Страница 8: ...Number DA 2 File Name PBESR_QuadCore_Manual Document Location S Product_Folders Manuals PBESR_QuadCore Original Document Created Chris Hett 2009 01 22 Revision History Chris Hett 2009 02 03 Edited Figure 1 to more correctly display board architecture with timing based on Core0 Updated formatting www spincore com 8 02 17 09 ...

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