PulseBlasterESR QuadCore 250 (Turbo)
I. Introduction
Product Overview
The SpinCore PulseBlasterESR QuadCore 250 (Turbo) is a 4-Core PulseBlaster design implemented on
PulseBlasterESR PCI boards. The 4-Core design uses four of SpinCore's proprietary PulseBlaster processor
cores on a single chip. This new design allows the user to program and run independent programs on each core,
in parallel, while maintaining precise timing synchronization between the cores.
Each individual PulseBlaster core has one output bit (flag/channel) available as a TTL signal on the
corresponding BNC connector of the PC bracket. For example, the output bit for Core0 is on the BNC0
connector closest to the PCI slot as seen in Figure 1.
Figure 1
: SpinCore PulseBlasterESR QuadCore design topology and connector locations. All four
PulseBlaster cores and triggering circuitry have been implemented on a single chip.
All four cores are driven by the same, single clock source, 250 MHz. They can be synchronized to start at
the same time and run four unique pulse programs/sequences concurrently. At 250 MHz, the available
resolution of each pulse/delay/interval is 4 ns (one clock cycle), the minimum pulse/delay/interval length is 5
clock cycles, or 20 ns, and the maximum pulse/delay/interval length is 2
29
clock cycles (~2.15 seconds). Each
core has 1k (1024) memory words available for writing pulse programs, i.e., there can be up to 1024 lines in your
pulse program per core.
The basic architecture of the individual PulseBlaster processor cores is described in multiple documents,
including the Manuals for PulseBlaster and PulseBlasterESR boards, available on-line at the SpinCore's website
Programming Paradigm
Each core can be individually programmed with an arbitrary sequence of intervals. Each interval can be of
unique length, and up to 1024 intervals can be accommodated per sequence. Since each interval can be a
pulse or a delay, the programming of each core involves the loading of two basic parameters per interval: the
output state (logical O or 1), and the duration of the state (in nanoseconds, microseconds, milliseconds).
Each core can be independently selected for programming and program execution. The low-level interaction
is through the set of specific functions in the dedicated Application Programming Interface (API) package called
SpinAPI, available for download on SpinCore's website www.spincore.com. Virtually any higher-level
application package (Java, C, Matlab, LabVIEW, Visual Basic, etc.) can interact with the board through the
provided SpinAPI functions.
www.spincore.com
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02/17/09
BNC3
BNC2
BNC1
BNC0
Clock
and
triggering
circuitry
PulseBlaster Core1
PulseBlaster Core2
PulseBlaster Core3
PulseBlaster Core0
