PulseBlasterESR-PRO-200-cPCI
II. Device Description and Specifications
Device Overview
System Architecture
The major building blocks of the PulseBlaster processor core are the SRAM memory, the microcontroller
core (uPC), the integrated bus controller (IBC), the counter, and the output buffers. All components are
located on a single silicon chip, making the design a System-on-a-Chip (SOC). User control of the device is
provided through the integrated bus controller (IBC) using the CompactPCI bus. The figure below shows the
block diagram of the PulseBlaster processor core.
Output Signals
Pulse sequences are output digitally using 3.3 V Low Voltage TTL (LVTTL). If the channel is on, then the
device will output 3.3 V unterminated, and if the channel is off, the device will output 0.0 V, unterminated.
Each channel is capable of delivering up to
25 mA per channel. If more output current is necessary, the
individual channels can be driven in parallel.
Outputs are available on BNC connectors and IDC headers. The BNC connectors are impedance
matched to 50 Ω and are located on the mounting bracket. All outputs are available on IDC headers located
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2017/01/24
Figure 1:
Block Diagram of the PulseBlaster processor core. All the components
are placed on a single silicon chip, making the design a System-on-a-
Programmable-Chip (SOPC). The clock oscillator signal is derived from an on-chip
PLL circuit typically using a 50 MHz on-board reference clock.
CompactPCI bus
