PulseBlaster
Waiting
– The PulseBlaster device has encountered a WAIT Op Code and is waiting for the next
trigger (either hardware or software) to resume operation. Note that the Running bit will also be
high during a WAIT state.
Shrouded IDC Connector HW Trig/Reset
This is an input connector, for hardware triggering (HW_Trigger) and resetting (HW_Reset).
CAUTION:
Applying voltages to the input pins that are greater than 3.3V or less than 0V
will damage the PulseBlaster
.
Pin Assignments
Pin#
Pin#
1
GND
2
HW_Trigger_H
3
GND
4
HW_Trigger_H
5
GND
6
HW_Reset_H
7
GND
8
HW_Reset
9
GND
10
HW_Trigger
Table 5:
Pinout for HW_TRIG/RESET IDC Connector on SP17 and PulseBlaster PCIe boards.
Note that for all board models the IDC pins are enumerated in the manner shown by Figure 11,
below. Pin 1 is marked on the board and the rest of the pins follow in this fashion (for the 26 pin IDC
connectors, the pin numbers simply continue in this pattern until pin 26).
SP17 and PulseBlaster PCIe boards come with three hardware trigger pins.
HW_Trigger
is
pulled to high voltage (3.3V) on the board and can be triggered by a low pulse (or shorting to GND,
e.g., pin 9). The two
HW_Trigger_H
pins are pulled to low voltage (ground) on the board and can be
triggered with a high voltage pulse (to 3.3V). When the falling edge is detected (or rising edge on
HW_Trigger_H), and the program is idle, code execution is triggered. If the program is idle due to a
WAIT instruction, the HW_Trigger will cause the program to continue to the next instruction. If the
program is idle due to a STOP instruction or a HW_Reset signal, the HW_Trigger will start execution
from the beginning of the program. If the STOP instruction was used, a HW_Reset or software reset
(pb_reset()) needs to be applied prior to the HW_Trigger.
2021/03/22
22
Figure 11:
IDC connector pin enumeration.