Spectrum Digital TMS320DM365, Техническое описание

Страница: 15 / 140

Spectrum Digital, Inc
1-5
1.4 Memory Map
The DM365 processor has a byte addressable address space. There are some
limitations to byte addressing which are determined by peripheral interconnection to the
DM365 device. Program code and data can be placed anywhere in the unified address
space. Addresses are multiple sizes depending on hardware implementation. Refer to
the appropriate device data sheets for more details.
The memory map shows the address space of a generic DM365 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The other EMIF has 2 separate addressable regions called chip
enable spaces (CE0 & CE1). The NAND Flash, one NAND, and CPLD are mapped into
these chip enable spaces.
DM365 EVM
Address
0x00000000
0x00008000
0x00010000
0x04000000
0x20000000
0x80000000
CE1
DDR EMIF
Figure 1-3, Memory Map, DM365 EVM
ARM Instruction RAM
ARM Instruction ROM
CE0 - ASYNC EMIF (Data)
0x02000000
Memory Map Address Space
0x8FFFFFFF
DDR EMIF Control Regs
ARM RAM (Data)
CFG Bus Peripherals
0x01C00000
0x0000BFFF
0x00017FFF
0x01FFFFFF
0x03FFFFFF
0x05FFFFFF
0x2007FFFF
0x00007FFF
0x87FFFFFF
0x88000000
DDR Expansion
(reserved)