Spectrum Digital, Inc
2-3
2.1.2 CPLD Registers
The 4 CPLD memory-mapped registers allows users to control CPLD functions in
software. On the 6713 DSK the registers are primarily used to access the LEDs and
DIP switches and control the daughter card interface. The registers are mapped into
EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a
simple asynchronous memory interface. The following table gives a high level
overview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 4 registers in CPLD.
2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or
off to allow the user to interact with the DSK. The DIP switches are read by reading the
top 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 1: CPLD Register Definitions
Offset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
USER_REG
USR_SW3
R
USR_SW2
R
USR_SW1
R
USR_SW0
R
USR_LED3
R/W
0(Off)
USR_LED2
R/W
0(Off)
USR_LED1
R/W
0(Off)
USR_LED0
R/W
0(Off)
1
DC_REG
DC_DET
R
0
DC_STAT1
R
DC_STAT0
R
DC_RST
R
0(No reset)
0
DC_CNTL1
R/W
0(low)
DC_CNTL0
R/W
0(low)
4
VERSION
CPLD_VER[3.0]
R
0
BOARD VERSION[2.0]
R
6
MISC
SCR_5
R/W
0
SCR_4
R/W
0
SCR_3
R/W
0
SCR_2
R/W
0
SCR_1
R/W
0
FLASH_PAGE
R/W
0
(Flash A19=0)
McBSP1
ON/OFF
Board
R/W
0
(Onboard)
McBSP0
ON/OFF
Board
R/W
0
(Onboard)
Table 2: CPLD USER_REG Register
Bit
Name
R/W
Description
7
USER_SW3
R
User DIP Switch 3(1 = Off, 0 = On)
6
USER_SW2
R
User DIP Switch 2(1 = Off, 0 = On)
5
USER_SW1
R
User DIP Switch 1(1 = Off, 0 = On)
4
USER_SW0
R
User DIP Switch 0(1 = Off, 0 = On)
3
USER_LED3
R/W
User-defined LED 3 Control (0 = Off, 1 = On)
2
USER_LED2
R/W
User-defined LED 2 Control (0 = Off, 1 = On)
1
USER_LED1
R/W
User-defined LED 1 Control (0 = Off, 1 = On)
0
USER_LED0
R/W
User-defined LED 0 Control (0 = Off, 1 = On)
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