Spectrum Digital, Inc
2-10
eZdsp
TM
F2808 Technical Reference
2.3.4 P5/P9, Analog Interface
The position of the 30 pins on the P5/P9 connectors are shown in the diagram below
as viewed from the top of the eZdsp.
The definition of P5/P9 signals are shown in the table below.
* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.
Table 4: P5/P9, Analog Interface Connector
P5
Pin #
Signal
P9
Pin #
Signal
P9
Pin #
Signal
1
ADCINB0
1
GND
2
ADCINA0
2
ADCINB1
3
GND
4
ADCINA1
3
ADCINB2
5
GND
6
ADCINA2
4
ADCINB3
7
GND
8
ADCINA3
5
ADCINB4
9
GND
10
ADCINA4
6
ADCINB5
11
GND
12
ADCINA5
7
ADCINB6
13
GND
14
ADCINA6
8
ADCINB7
15
GND
16
ADCINA7
9
ADCREFM
17
GND
18
VREFLO
*
10
ADCREFP
19
GND
20
No connect
P9
Figure 2-6, Connector P5/P9 Pin Locations
7
5
3
1
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
ANALOG
1
2
3
4
5
6
7
8
9
10
P5
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