BIOS Setup Utility
SY-V6BE+
47
CHIPSET FEATURES SETUP
CHIPSET
FEATURES
Setting
Description
Note
SDRAM 10ns
SDRAM 8ns
Normal
Medium
Fast
Slot 0 DRAM
Timing
Slot 1 DRAM
Timing
Slot 2 DRAM
Timing
Turbo
Choose DRAM Timing
Default
SDRAM Cycle
Length
3
2
When synchronous DRAM is
installed, the number of
clock cycles of CAS latency
depends on the DRAM
timing. Do not reset this field
from the default value
specified by the system
designer.
Default
Disabled
Default
Memory Hole
15M -16M Some interface cards will
map their ROM address to
this area. If this occurs,
select 15M –16M in this
field.
Disabled
When disabled, CPU bus
will be occupied during the
entire PCI operation period
.
Default
Concurrent
PCI/Host
Enabled
Disabled
Default
Video RAM
Cacheable
Enabled
The ROM area A0000-
BFFFF is cacheable.
AGP Aperture
Size
64
4-128MB
AGP could use the DRAM
as its video RAM. Choose
the DRAM size that you
wish to allocate as video
RAM.
Default
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