BIOS Setup Utility
SY-P4VGA
47
DRAM Control
Setting
Description
Note
By SPD
Default
DRAM Clock
Manual
This item allows you to control
the DRAM clock speed.
By SPD
Default
DRAM Timing
Manual
If enable the DRAM will auto
detect the DRAM timing.
3
2.5
Default
2
SDRAM CAS
Latency
1.5
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency depends
on the DRAM timing. Do not
reset this field from the default
value specified by the system
designer.
Disabled
Default
2 Bank
Bank Interleave
4 Bank
Increase DRAM performance.
2T
Precharge to
Active(Trp)
3T
Increase DRAM performance.
Default
6T
Default
Active to
Precharge(Tras)
7T
Increase DRAM performance.
2T
Active to CMD
(Trcd)
3T
Increase DRAM performance.
Default
2T Command
Default
DRAM Command
Rate
1T Command
Increase DRAM performance.
4
Default
DRAM Burst
Length
8
Increase DRAM performance.
Medium
Default
Slow
CPU read DRAM
Mode
Fast
Increase DRAM performance.
