35
XP-ZR810
• IC601 CXD3048R RF AMP, DSP, DIGITAL SERVO PROCESSOR, D-RAM CONTROLLER (MAIN Board)
Pin No.
1
2
3 to 6
7
8
9
10
11 to 13
14
15 to 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53, 54
55
56
57
58
I/O
O
O
I/O
O
O
O
O
O
—
O
I
—
I
I
O
I
I
I
O
O
I
I
I
I
O
—
I
I
O
O
O
O
I
I
—
O
O
—
—
I
O
—
—
O
O
—
O
O
—
I
Pin Name
XRAS
XWE
D1, D0, D3, D2
DCLK
DCKE
XCAS
WFCK/DQM
A9 to A7
DVSS
A6 to A4
XRDE
VDD0
CLOK
SDTO
SENS
XLAT
XSOE
SYSM
WDCK
SCOR
XRST
PWMI
XQOK
XWRE
R8M
VSS0
SQCK
SCLK
SQSO
XEMP
XWIH
SBSO
EXCL
XTSL
HVSS
HPL
HPR
HPVDD
XVDD
XTAI
XTAO
XVSS
AVDD1
AOUT1
VREFL
AVSS1, AVSS2
VREFR
AOUT2
AVDD2
TES1
Description
Low address strobe signal output to the D-RAM
Data input enable signal output to the D-RAM
Two-way data bus with the D-RAM
Not used (open)
Not used (open)
Column address strobe signal output to the D-RAM
Not used (open)
Address signal output to the D-RAM
Ground terminal
Address signal output to the D-RAM
D-RAM read enable signal input
Power supply terminal
Serial data transfer clock input from the TMP91CY28FG
Serial data input from the TMP91CY28FG
Serial data output to the TMP91CY28FG
Serial data latch pulse signal input from the TMP91CY28FG
Serial data output enable signal input from the TMP91CY28FG
Analog muting on/off control signal input from the TMP91CY28FG “H”: muting on
Not used (open)
Subcode sync (S0+S1) detection signal output to the TMP91CY28FG
Reset signal input from the TMP91CY28FG “L”: reset
Not used (connected to the ground)
Not used (fixed at “L”)
Not used (fixed at “L”)
System clock output to the TMP91CY28FG
Ground terminal
SQSO readout clock input (not used (fixed at “H”))
SENS serial data read clock input (not used (fixed at “H”))
Not used (open)
Not used (open)
Not used (open)
Not used (open)
SBSO readout clock input (not used (fixed at “L”))
Input terminal for the system clock frequency setting (fixed at “L”)
Ground terminal
Not used (open)
Not used (open)
Power supply terminal
Power supply terminal
System clock input (16.934 MHz)
System clock output (16.934 MHz)
Ground terminal
Power supply terminal
L-ch analog audio signal output
L-ch reference voltage output
Ground terminal
R-ch reference voltage output
R-ch analog audio signal output
Power supply terminal
Input terminal for the test (fixed at “L”)
