NET-28/28A (1/3)
J1601
J1602
VCO131/X1401/
VC1402/VC1401
TG Circuit
27M/74M
148M
148M
148M
148M
148M
User IF0[20:1]
User IF1[20:1]
User IF2[20:1]
User IF3[20:1]
IC1001
Neptunell-A
IC1501
PHY-A
XAUI P0-Lane[4:1]
XAUI P1-Lane[4:1]
J2401
J2402
VCO211/X2201/
VC2202/VC2201
TG Block
27M/74M
148M
148M
148M
148M
148M
User IF5[20:1]
User IF6[20:1]
User IF7[20:1]
User IF8[20:1]
IC1801
Neptunell-B
IC2301
PHY-B
XAUI P0-Lane[4:1]
XAUI P1-Lane[4:1]
F/V/H
F/V/H
F/V/H
F/V/H
User IF_0
User IF_1
User IF_2
User IF_3
User IF_5
User IF_6
User IF_7
User IF_8
TBC
TBC
UIF 0
UIF 1
UIF 2
UIF 3
UIF 5
UIF 6
UIF 7
UIF 8
P/S
P/S
(SDI)
REF GEN
IC301 FPGA-A
VCO391/X4001/
VC4002/VC4001
TG Block
IC3601
Neptunell-C
User IF0[20:1]
User IF1[20:1]
User IF2[20:1]
User IF3[20:1]
IC4401
Neptunell-D
User IF6[20:1]
User IF7[20:1]
User IF8[20:1]
User IF5[20:1]
REF GEN
S/P
XAUI P0-Lane[4:1]
XAUI P1-Lane[4:1]
XAUI P0-Lane[4:1]
XAUI P1-Lane[4:1]
IC4101
PHY-C
IC4901
PHY-D
J4201
J4202
J5001
J5002
27M/74M
VCO391/X4001/
VC4002/VC4001
TG Block
148M
27M/74M
148M
IC301
FPGA
REFCLK_CH1-4_P/N
XCVRCLK_CH1-4_P/N
REFCLK_CH5-8_P/N
XCVRCLK_CH5-8_P/N
IC5401
Clock
Matrix
FPGA-A_VCLK74M P/N
FPGA-A_VCLK148M P/N
FPGA-A_VCLK27M P/N
FPGA-A_VCLK148.5M P/N
IC2901
FPGA
REFCLK_CH9-12_P/N
XCVRCLK_CH9-12_P/N
REFCLK_CH13-16_P/N
XCVRCLK_CH13-16_P/N
IC5404
Clock
Matrix
FPGA-B_VCLK74M P/N
FPGA-B_VCLK148M P/N
FPGA-B_VCLK27M P/N
FPGA-B_VCLK148.5M P/N
IC5402
Clock Jitter
Cleaner
IC5402
Clock Jitter
Cleaner
IC2901 FPGA-B
TBC
SDI 09-10
SDI 11-12
XCVRCLK_CH9-12_P/N
REFCLK_CH9-12_P/N
SDI 13-16
XCVRCLK_CH13-16_P/N
REFCLK_CH13-16_P/N
Buffer
IC110
IC108
TOP P/N
VCLK 1 P/N
VCLK 2 P/N
CNF1
CNM1
REFCLK_CH1-4_P/N
XCVRCLK_CH1-4_P/N
REFCLK_CH5-8_P/N
XCVRCLK_CH5-8_P/N
SDI 0
SDI 1
SDI 2
SDI 3
SDI 5
SDI 6
SDI 7
SDI 8
SDI 09-10
XVS-8000-C/XVS-8000
8-9
Содержание XKS-8160
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Страница 45: ...Section 5 Maintenance Menu This section will be described soon XVS 8000 C XVS 8000 5 1 ...
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Страница 102: ...XVS 8000 C SY XVS 8000 SY XVS 8000 CN J E 9 878 693 01 Sony Corporation Printed in Japan 2016 1 08 2016 ...