24
MC-S50
Pin No.
Pin Name
I/O
Description
96
X1
O
System clock output terminal (16.9344MHz)
97
X2/CLKIN
I
System clock input terminal (16.9344MHz)
98
RS
I
Reset signal input to the CPU (IC801) “L”: reset
99 to 104
D0 to D5
I/O
Two-way data bus with the flash ROM (IC602) and USB controller (IC901)
105
A16
—
Address signal terminal Not used (open)
106
DVSS
—
Ground terminal
107 to 110
A17 to A20
—
Address signal terminal Not used (open)
111
CVSS
—
Ground terminal
112
DVDD
—
Power supply terminal (+3.2V)
113, 114
D6, D7
I/O
Two-way data bus with the flash ROM (IC602) and USB controller (IC901)
115 to 119
D8 to D12
I/O
Two-way data bus Not used (open)
120
HD4
O
Chip select signal output to the flash ROM (IC602)
121 to 123
D13 to D15
I/O
Two-way data bus Not used (open)
124
HD5
O
Audio system power ON/OFF control signal output terminal “H”: ON
125
CVDD
—
Power supply terminal (+1.5V)
126
CVSS
—
Ground terminal
127
HDS1
I
Data signal input terminal Not used (fixed at “H”)
128
DVSS
—
Ground terminal
129
HDS2
I
Data signal input terminal Not used (fixed at “H”)
130
DVDD
—
Power supply terminal (+3.2V)
131 to 134
A0 to A3
O
Address signal output to the USB controller (IC901)
135
HD6
O
Reset signal output to the D/A converter (IC302) “L”: reset
136 to 139
A4 to A7
O
Address signal output to the USB controller (IC901)
140, 141
A8, A9
—
Address signal terminal Not used (open)
142
CVDD
—
Power supply terminal (+1.5V)
143
A21
—
Address signal terminal Not used (open)
144
DVSS
—
Ground terminal