Sony SWF-BR100, Руководство по обслуживанию

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SWF-BR100
SWF-BR100
22 22
• Waveforms
– MAIN Board –
1
IC111 qa (XOUT)
1 V/DIV, 50 ns/DIV
125 ns
2.9 Vp-p
2
IC103 9 (2Q)
1 V/DIV, 50 ns/DIV
81 ns
4 Vp-p
3
IC105 qf (XFSOOUT)
1 V/DIV, 10 ns/DIV
20.6 ns
2.9 Vp-p
20.8
P
s
3.3 Vp-p
4 IC105
wl
(LRCK)
1 V/DIV, 10
P
s/DIV
326 ns
3.3 Vp-p
5 IC105
e;
(BCK)
1 V/DIV, 200 ns/DIV
6 IC107
4
1 V/DIV, 10 ns/DIV
20.8 ns
3 Vp-p
• IC Block Diagrams
– MAIN Board –
IC101 PST8435UL
GND 1
VDD 2
+
–
VREF
OUT 4
CD 3
IC103 TC74LCX74FT (EKJ)
IC104 CXD9981TN
14
1 2 3 4 5 6 7
13 12 11 10 9 8
VCC
GND
CK
CLR
CK
CLR
Q
PR
Q
Q
PR
Q
D
D
1
2
3
4
5
6
INTERNAL PULLUP
RESISTORS TO VREG
PROTECTION
AND
I/O LOGIC
OVERLOAD
PROTECTION
PWM
RCV.
CTRL TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
44
43
42
41
40
39
38
37
35
27
16
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
26
33
34
32
31
30
8
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
29
24
25
23
36
18
19
20
21
22
PWM
RCV.
CTRL
TIMING
GATE
DRIVE
BTL/PBTL-CONFIGURATION
PULLDOWN RESISTOR
27
28
POWER
ON
RESET
TEMP.
SENSE
UNDER-
VOLTAGE
PROTECTION
4
VREG
I-SENSE
13
14
15
17
12
7
11
9
10
M3
M2
M1
PWM_C
/RESET_CD
GVDD_B
/DTW
NC
NC
/SD
PWM_A
/RESET_AB
GND
AGND
VREF
PWM_B
OC_ADJ
PWM_D
NC
NC
VDD
GVDD_C
NC
BST_D
GVDD_D
OUT_D
PVDD_D
PVDD_D
GND_C
GND_D
BST_C
PVDD_C
OUT_C
OUT_B
PVDD_B
BST_B
GND_A
GND_B
PVDD_A
PVDD_A
OUT_A
GVDD_A
BST_A
NC
4