
30
STR-KS500
DIGITAL BOARD IC1601 MB90488BPF-G-196E1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DATAO
I
Audio serial data input from the digital audio interface receiver
2
GP9
I
Read ready signal input from the audio digital signal processor
3
BST
O
Boot strap signal output to the audio digital signal processor
4
HCS
O
Chip select signal output to the audio digital signal processor
5
HACN
I
Acknowledge signal input from the audio digital signal processor
6
XRST
O
System reset signal output to the audio digital signal processor "L": reset
7
PM
O
PLL initialize signal output to the audio digital signal processor "L": initialize
8
GP12
O
Write signal output to the audio digital signal processor
9
PCM1803_ RST
O
System reset signal output to the A/D converter "L": reset
10
PCM1602_ RST
O
System reset signal output to the D/A converter "L": reset
11
VSS
-
Ground terminal
12
PCM1602_ ML
O
Serial data latch pulse signal output to the D/A converter
13
PCM1602_ MC
O
Serial data transfer clock signal output to the D/A converter
14
PCM1602_ MDI
O
Serial data output to the D/A converter
15
PCM1602_ MDO
I
Serial data input from the D/A converter
16
TUNER_CLK
O
Serial data transfer clock signal output to the tuner
17
TUNER_DATA
O
Serial data output to the tuner
18
HDOUT
I
Serial data input from the audio digital signal processor
19
HDIN
O
Serial data output to the audio digital signal processor
20
HCLK
O
Serial data transfer clock signal output to the audio digital signal processor
21
VOL_CLK
O
Serial data transfer clock signal output to the electrical volume
22
VOL_DATA
O
Serial data output to the electrical volume
23
VCC5
-
Power supply terminal (+3.3V)
24
ANA/DIG
O
Analog/digital selection signal output terminal Not used
25, 26
NOT IN USE
O
Not used
27, 28
FLASH2, FLASH1
O
Flash programming signal output terminal
29
SDA
I/O
Two-way data bus with the EEPROM
30, 31
NO USE
O
Not used
32
NOT IN USE
O
Not used
33
SCL
O
Serial data transfer clock signal output to the EEPROM
Reference voltage (+3.3V) input terminal
Front panel key input terminal (A/D input)
RDS signal input from the tuner
44
MODEL
I
Setting terminal for the model (A/D input)
45
VERSION
I
Setting terminal for the destination (A/D input)
46
FAN-HI-DETECT
I
Fan motor hi-speed detection signal input terminal
47
NO USE
O
Not used
48
STOP
I
AC off detection signal input terminal "L": AC off
49
MD0
I
CPU operation mode setting signal input terminal
50
MD1
I
Setting terminal for the CPU operation mode Fixed at "H" in this set
51
MD2
I
CPU operation mode setting signal input terminal
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299