STR-DH800
50
Pin No.
Pin Name
I/O
Description
123
SIRCS
I
SIRCS signal input from the remote control receiver
124
DIR_CE
O
Chip enable signal output to the digital audio interface receiver
125
DIR_DO
I
Serial data input from the digital audio interface receiver
126
DIR_ERROR
I
PLL lock error signal and data error
fl
ag input from the digital audio interface receiver
127 to 130
MD3 to MD0
-
Mode setting terminal Fixed at “L” in this set
131
INITX
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
132
VSS_(GND)
-
Ground terminal
133
VCC5
-
Power supply terminal (+3.3V)
134
SI_Rx
I
Serial data input terminal (use for Firmware Flash Program)
135
SO_Tx
O
Serial data output terminal (use for Firmware Flash Program)
136
NO_USE
-
Not used
137
RST_TRIGGER
O
Reset signal output terminal for the system controller “L”: reset
138
EEPROM_SDA
I/O
Two-way data bus with the EEPROM
139
EEPROM_SCL
O
Serial data transfer clock signal output to the EEPROM
140
FL_LATCH
O
Serial data latch pulse signal output to the
fl
uorescent indicator tube
141
FL_DATA
O
Serial data latch pulse signal output to the
fl
uorescent indicator tube
142
FL_CLK
O
Serial data transfer clock signal output to the
fl
uorescent indicator tube
143
SIRIUS_MISO
I
Serial data input from the SIRIUS socket (US and Canadian models only)
144
SIRIUS_MOSI
O
Serial data output to the SIRIUS socket (US and Canadian models only)
145
SIRIUS_POWER_ENA
O
Power detection signal output to the SIRIUS socket (US and Canadian models only)
146
VSS_(GND)
-
Ground terminal
147
VCC5
-
Power supply terminal (+3.3V)
148
DMPORT_MISO
I
Serial data input from the DMPORT connector
149
DMPORT_MOSI
O
Serial data output to the DMPORT connector
150
DMPORT_DETECT
I
DMPORT adapter connection detection signal input terminal
“H”: DMPORT adapter is connected
151
SPI0_MISO
I
Serial data input from the serial
fl
ash and DSP
152
SPI0_MOSI
O
Serial data output to the serial
fl
ash and DSP
153
SPI0_CLK
O
Serial data transfer clock signal output to the serial
fl
ash and DSP
154 to 156
NO_USE
-
Not used
157
DIR_CKST#
I
Clock selection signal input from the digital audio interface receiver
158
DIR_SIGNAL
I
Audio serial data input from the digital audio interface receiver
159
DIGI_DATA_MUTE
O
Muting control signal output terminal
160
ANA_DIGI
O
Analog/digital selection signal output terminal
161
VSS_(GND)
-
Ground terminal
162
VCC5
-
Power supply terminal (+3.3V)
163
TUNER_RDS_INT
(CLK)
I
RDS serial data transfer clock signal input from the tuner (FM/AM)
(AEP and UK models only)
164, 165
NO_USE
-
Not used
166
DSP_INT
I
Interrupt signal input from the DSP
167, 168
NO_USE
-
Not used
169
FSRATE
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
170
DIR_HDMI_SELECT
O
Digital audio interface receiver/HDMI receiver signal selection signal output terminal
171
SPI0_ENA
O
Chip enable signal output to the DSP
172
SFLASH_CE#
O
Chip enable signal output to the serial
fl
ash
173
SFLASH_HOLD
O
Hold signal output to the serial
fl
ash
174
SPI0_CS#
O
Chip select signal output to the DSP
175
DSP_RESET
O
Reset signal output to the DSP “L”: reset
176
VCC5
-
Power supply terminal (+3.3V)
