STR-DA9000ES
26
26
6-4.
BLOCK DIAGRAM – I. LINK Section –
HD0 – HD7
51
HCNTL0
52
HCNTL1
19
AKE_XF
21
HRDY
22
XHAS
23
XHDS1
24
XHDS2
25
XHCS
26
XRS
54
HRW
53
HBIL
I2C-DATA
I2C-CLK
30
IIC DATA
29
IIC CLK
12
RESET
39 HCNTL0
46 HCNTL1
27 XF
55 HRDY
13 HAS
127 HDS1
129 HDS2
17 HCS
98 RS
18 HR/W
62 HBIL
53
50
51
52
XRDY
25
PLLCKI
XCS
XWR
XRD
79
78
XCAS
XRAS
80
81
XOE
XWE
39
49
RDY
CXD3270_XCS
122
119
XRESETO
PWD
90
89
PHY_RST
PHY_BIAS
165
XRESETL
92 LINK_RST
27
22
44
A1 – A13
D0 – D15
47 – 40, 38 – 31
DATA0 – DATA15
55 – 62
88 – 73
7 – 1, 100
ADDRESS1 –
ADDRESS8
EEPROM
IC3001
VCO
IC3005
D0 – D7
D0 – D7
D0 – D15
D0 – D15
A1 – A8
A1 – A13
A1 – A13
A0 – A12
WE
OE
RD
20
48
CE
EEP_CS
11 – 13,
15 – 19
DT0 – DT15
99 – 92,
90 – 83
71 – 65, 63,
61 – 57
HD0 – HD7
58, 69, 81, 95,
120, 124, 135, 6
10 – 2, 21,
25 – 23
14
TRA1P
I. LINK SYSTEM
CONTROLLER
IC3002
I. LINK INTERFACE
IC3003
X3001
24.576MHz
I. LINK DSP
IC3012
(Page 25)
BIAS
TAIP
TAIN
TBIP
TBIN
4
J3002
i. LINK S200
AUDIO IN
1
2
3
15
DI1O
16
DI2O
19
DI5O
20
DI6O
17
DI3O
18
DI4O
22
(Page 28)
ADDRESS BUS
DA
TA BUS
97
96
X3003
20MHz
X2/CLKIN
X1
15
13
X3002
10MHz
XIN
XOUT
RESET SWITCH
IC3011
143
TRA1N
142
TRB1P
141
TRB1N
145
DSD-L
DSD-R
DSD-SL
DSD-SR
DSD-C
DSD-W
172 LRCKO
LRCK
171 SACKO
BCK
MILES RESET
MILES AUDIO
164 DOUT
958OUT
3
VALIB OUT
64FS
27 FSS12 OUT
I512
167 FSS12
22.5792
LEVEL SHIFT
IC3013
21
(Page 27)
9
(Page 24)
130
129
XI
XO
D0 – D15
2 – 5, 7 – 10,
41 – 44, 46 – 49
A0 – A9
76 – 71,
69 – 66
A0 – A9
21 – 24,
27 – 32
SD-RAM
IC3008
18 XRAS
34 UCAS
35 LCAS
17 XWE
33 XOE
174
ERR_OUT
24
SYTOUT
SWITCHING
IC3007 (1/2)
DIVIDER
IC3006
35 ERR CLR
2
CK
3 VCOO
7
ENP
ERROR-3210
9
LOAD
1
CLR
15
C0
10
UN-MUTE
DIVIDER
IC3009
IC3007 (2/2)
2
CK
7
ENP
9
LOAD
1
CLR
12
QC
10
ENT
ERROR-3210
15
5 FINB
4 FINA
10
VCOX
23
REFOUT
DATA
(Page 33)
23
46 WR
18 MIES AUDIO
(Page 25)
11
I512 OFF
(Page 25)
19
• SIGNAL PATH
: AUDIO (DIGITAL)
