Sony STR-DA9000ES - Fm Stereo/fm-am Receiver, Руководство по обслуживанию

Страница: 144 / 202

144
STR-DA9000ES
Pin No. Pin Name I/O Description
53, 54 BFSX0, BFSX2 I Frame sync signal input terminal Not used
55 HRDY O Ready signal output to the i. link system controller
56 DVDD (3.3V) —
Power supply terminal (+3.3V)
57 VSS —
Ground terminal
58 HD0 I/O
Two-way data bus with the i. link system controller
59, 60 BDX0, BDX2 O
Serial data output terminal Not used
61 IACK O
Interrupt acknowledge signal output terminal Not used
62 HBIL I
Byte identification signal input from the i. link system controller
63
NMI I Non-maskable interrupt input terminal Not used
64, 65 INT0, INT1 I
Interrupt signal input terminal Not used
66 INT2 I
Interrupt signal input from the HINT/TOUT1 (
ta
pin)
67 INT3 I
Interrupt signal input terminal Not used
68 CVDD (1.8V) —
Power supply terminal (+1.8V)
69 HD1 I/O
Two-way data bus with the i. link system controller
70 VSS —
Ground terminal
71 BCLKX1 I
Transmit clock signal input terminal Not used
72 VSS —
Ground terminal
73 BFSX1 I
Frame sync signal input terminal Not used
74 BDX1 O
Serial data output terminal Not used
75 DVDD (3.3V) —
Power supply terminal (+3.3V)
76 VSS —
Ground terminal
77 to 79
CLKMD1 to
CLKMD3
I
Clock mode selection signal input terminal Not used
80 HPI16 I
HPI 16 bit selection signal input terminal Not used
81 HD2 I/O
Two-way data bus with the i. link system controller
82 TOUT0 O
Timer output terminal Not used
83 EMU0 I
Not used
84 EMU1/OFF I
Not used
85 TDO O
Not used
86 TDI I
Not used
87 TRST I
Not used
88 TCK I
Not used
89 TMS I
Not used
90 VSS —
Ground terminal
91 CVDD (1.8V) —
Power supply terminal (+1.8V)
92 HPIENA I
HPI module selection signal input terminal Not used
93 VSS —
Ground terminal
94 CLKOUT O
Master clock signal output terminal Not used
95 HD3 I/O
Two-way data bus with the i. link system controller
96 X1 O
System clock output terminal (20 MHz)
97 X2/CLKIN I
System clock input terminal (20 MHz)
98 RS I
Reset signal input from the i. link system controller “L”: reset
99 to 104 D0 to D5 I/O
Two-way data bus terminal Not used
105 A16 O
Address signal output terminal Not used
106 VSS —
Ground terminal
107 to 110 A17 to A20 O
Address signal output terminal Not used