Sony SS-US501, Руководство по обслуживанию

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26
SS-US501/SW-US501/UZ-US501
• IC Pin Function Description
DIGITAL BOARD IC501 TUSB3200ACPAH (USB CODEC)
Pin No. Pin Name I/O Description
1 PLLFILO O PLL loop filter output terminal
2 AVDD — Power supply terminal (+3.3V) (analog system)
3 PWMO O PWM signal output terminal Not used
4 PLLO O PLL signal output terminal Not used
5 DVSS — Ground terminal (digital system)
6 PUR O USB data (+) output terminal
7 DP I USB data (+) input terminal
8 DM I USB data (–) input terminal
9 DVDD — Power supply terminal (+3.3V) (digital system)
10 MRST I Master reset signal input from the reset signal generator “L”: reset
11 TEST I Input terminal for the test mode
12 EXTEN I Input terminal for the external MCU mode
13 RSTO O Reset signal output terminal Not used
14 P3.0 — Not used
15 P3.1 O Master clock frequency selection signal output to the digital audio transmitter
16 DVSS — Ground terminal (digital system)
17 XINT I External interrupt signal input terminal “L” active Not used
18 P3.3 — Not used
19 P3.4 O Generation status signal output to the digital audio transmitter
20 P3.5 — Not used
21
DVDD
—
Power supply terminal (+3.3V) (digital system)
22 NC — Not used
23 PLLO O
PLL output enable signal output terminal Not used
24 P1.0 O Master clock frequency selection signal output to the digital audio transmitter
25, 26 P1.1, P1.2 — Not used
27
DVDD5
—
Power supply terminal (+5V) (digital system)
28 to 32 P1.3 to P1.7 — Not used
33 DVSS — Ground terminal (digital system)
34 BCK O
Audio serial data transfer clock signal output to the digital audio transmitter
35 LRCK O Frame sync signal output to the digital audio transmitter
36 DOUT1 O
Audio serial data output to the digital audio transmitter
37
DVDD
—
Power supply terminal (+3.3V) (digital system)
38 DOUT2 I
Audio serial data input terminal Not used
39 CRESET O Reset signal output terminal Not used
40 SDIN1 O Secondary channel enable signal output terminal Not used
41 SDA I/O Two-way data bus with the EEPROM
42 SCL O
Serial data transfer clock signal output to the EEPROM
43
DVDD5
—
Power supply terminal (+5V) (digital system)
44 MCLKO O Master clock signal output to the digital audio transmitter
45 MCLKO2 O Master clock signal output terminal Not used
46 DVSS — Ground terminal (digital system)
47, 48
MCLKI, MCLKI2
I Master clock signal input terminal Not used
49 AVSS — Ground terminal (analog system)
50
XTALO
O
System clock output terminal (6 MHz)
51
XTALI
I
System clock input terminal (6 MHz)
52
PLLFILI
I
PLL loop filter input terminal