Sony KP 48S70, Руководство по обучению

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VD Mute
Overview
Due to the fact that this set displays a true 16:9 picture in a cabinet with a
4:3 aspect ratio, the IK reference pulses and CC data contained in every
field need to be hidden. The VD Mute circuit does this. If correction were
not made, these lines would be visible at the top of a 16:9 picture. This
circuit takes the IK reference pulses and CC data and puts them into the
normal 4:3 overscan area when they are occurring by placing a pulse into
the vertical drive signal. Inputting the HBLK and VBLK into a series of two
programmable counters does this. These counters are set up so that the
pulse output is equivalent to 11 horizontal scanning lines. This pulse is
used to mute the V Drive signal.
VD Mute
Since this circuit only needs to be active when a 16:9 picture is being
displayed, an enable is necessary to allow the counters to count. This
signal is sent from IC1009/59 V Comp. IC1609 and IC1608 both have an
enable input that is tied to Deflection 5V at pin 10 ENP. This voltage must
be present for the circuit to operate.
The HBLK line is input to IC1609/2 CLR. This input appears to be for
Clear, but there is actually an error in the service manual. This line is
actually the CLK input but we will continue to call it CLR to avoid confu-
sion between this book and the service manual. The HBLK signal will be
33.7kHz when a 1080I signal is input and 31.5kHz if a 480P signal is
input. The VTIM signal that is input to IC1609/9 Load is always 60Hz.
These signals are always input to IC1609 so when the V Comp line goes
HIGH, the circuit begins to operate. IC1609/15 RCO is the carry output
and will be LOW for the first 14H of the VTIM signal. Its output is inverted
by IC1623 and input to IC1609/7 ENT, which is used to keep the outputs
from changing state. IC1609/11 QD is LOW for the first 7H of the VTIM
signal and HIGH for the rest.
The signal from IC1609/15 RCO is input to IC1608/9 Load. The signals
from IC1609/11 are input to IC1608/1 /CLR. /CLR disables the IC1608
outputs when it is LOW. Therefore for the first 7H, the output at IC1608/
12 will be LOW. When IC1608/1 goes HIGH, the outputs are enabled and
the signal at IC1608/12 goes HIGH. This is because when the /CLR input
is HIGH and the Load input is LOW, the output at Q2 will be the same
state as the C input, which is at IC1608/5. This pin is tied to 5 volts;
therefore, the output from IC1608/12 is HIGH. This output stays HIGH for
7H for this reason. When the Load input goes HIGH, the output continues
to remain HIGH for another 4H. This is because IC1608/11 Q3 output is
inverted and input to IC1608/7 ENT. When the Load input is HIGH and
the ENT input is LOW, the output does not change state. When the ENT
line returns to a HIGH, then the output at IC1608/12 goes LOW. This
gives us the 11H pulse necessary to hide the IK and CC Data lines.
When the signal from IC1608/12 is LOW, both Q1631 and Q1629 are
OFF. When these transistors are OFF, this circuit has no effect on the V
Drive signal. When signal from IC1608/12 goes HIGH, then Q1631 and
Q1629 both turn ON. Q1631 mutes the V Drive directly by placing C1651
near ground potential. Q1629 turns ON, allowing current to flow through
Q1621 B-E through D1634 to ground. This action causes Q1630 to turn
ON. This will mute the V Drive signal by placing C1647 close to ground
potential.
RGB Mute
The 4H pulse that is output from IC1608/7 is used to mute the RGB sig-
nals at the end of the 11H VD Mute. This is necessary because as the
beam begins to travel back to the top of the 16:9 picture, we do not want
to see any retrace lines that might occur if video were to start at this point.
Therefore this 4H pulse mutes the RGB signals to the picture tubes.
V Out
20v 5 ms
IC1608
2v 5 ms