Sony Ipels PCS-G50, Руководство по обслуживанию

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PCS-G50/G50P
3-7
SIRCS BLOCK [CPU-382, CN-2635]
This block, comprising level converters circuit of SIRCS
signal receiver, a SIRCS signal transmission buffer, and a
microcomputer for the SIRCS signal decoding/encoding,
decodes the SIRCS signal from a remote commander via
the camera units, and encodes the monitor control SIRCS
signal output for the IR repeater modules.
Power (PWR) Block [PS-686, CN-2635]
This block generates necessary voltages used in PCS-
PG50/PG50P from
+
19.5 VDC supplied by the AC
adapter. This block also supplies power to an external unit
(PCSA-CG70/CG70P, PCSA-DSB1S, PCSA-B768S/
B384S), and controls power ON/OFF of these units.
ISDN (BRI/PRI) Interface Block [CPU-382]
This block is an ISDN interface circuit that comprises a
driver, a receiver and a serial data transceiver for data
communication with PCSA-B768S/B384S.
USB Interface Block [CPU-382]
This block, comprising a bus controller being compliant
with the USB2.0 standard and a control IC that supplies the
power to the USB device, mainly detects USB devices and
processes data.
DSB Interface Block [CPU-382]
This block is a PCSA-DSB1S interface circuit. PCS-PG50/
PG50P is connected to PCSA-DSB1S with a special cable.
This block comprises the following:
.
Bidirectional data transmission block
Fast Ethernet Controllers (incorporating MAC/PHY)
Transformer
.
Analog video outputs (PCS-PG50/PG50P
→
PCSA-
DSB1S)
.
Audio line outputs (PCS-PG50/PG50P
→
PCS-DSB1S)
.
Audio microphone input (PCS-DSB1S
→
PCS-PG50/
PG50P)
. +
19.5 V DC power supply
CODEC Block [CPU-382, DSP-113]
This block consists of four blocks, each of which compris-
es a DSP and four 128-Mbit SDRAMs. DSP1 (ENC)
compresses video data sent from the Video FPGA block.
DSP2 (DEC) expands video data, generates a split screen
for multipoint connection, and outputs video signals to the
Video FPGA block. DSP3 (MUX) multiplexes video
signals and audio signals, compresses/expands audio
signals, generates outgoing/incoming sounds and operation
sounds, and sends/receives signals to/from the Echo
Canceller block. DSP3 also has a function to decode
received PC image signals and transfers them to the
graphic accelerator. DSP4 (MCU) divides video signals of
up to five points received during multipoint connection
into three multiplexed signals for full-screen display, and
transfers the signals to the Video FPGA block.
Audio Block [DSP-113]
This block, comprising an audio amplifier and A/D and D/
A converters, performs audio signal processing such as
selection of input audio signals, muting, A/D conversion
and D/A conversion. This block also sends/receives digital
signals to/from the Echo Canceller block.
Echo Canceller Block [CPU-382]
This block, comprising two DSPs, eliminates audio echoes,
suppresses noise in audio signals, and interfaces with the
CODEC DSP3 (MUX) as well as with the audio A/D and
D/A converters.
Memory Stick Block [CPU-382, MS-73]
This block is a memory stick interface circuit that compris-
es memory stick control ICs. This block controls power
supply to a memory stick, detects insertion of memory
stick, and also detects overcurrent.
LAN Interface Block [CPU-382]
This block is an Ethernet (10BASE-T/100BASE-TX)
interface circuit that comprises Fast Ethernet Controllers
(incorporating MAC/PHY) connected to the PCI bus and
an RJ45 connector with a built-in transformer.
VISCA Block [DSP-113]
This block, comprising a serial interface, a line driver, and
a line receiver, controls the camera unit.