30
ICD-S7
• IC7113 CXD3462ATQ (MEMORY CONTROL) (MAIN BOARD)
Pin No.
1
2
3
4 to 5
6
7
8
9
10
11 to 16
17
18
19 to 20
21
22
23
24
25
26
27 to 28
29
30
31
32
33
34
35
36
37
38
39 to 42
43
44
45
46 and 47
48
49
50
51
52
53 to 56
57
58
59
60
61
62 to 64
I/O
I
—
I
—
I/O
—
—
I
—
—
I
—
—
I
—
O
I
—
—
—
—
—
—
—
—
—
—
—
I
—
I/O
—
—
—
O
—
O
O
O
O
I/O
—
—
—
I
—
I
Description
MS (FLASH) number setup of chip loading input “L” : 1 chip, “H” : 2chip (fixed at “L”)
GND
I/F serial bus state input
Not used
I/F serial data input and output
Not used
Power supply
I/F serial clock input
GND
Not used
Write protection switch connection pin
Not used
Not used
Reset
Power supply
Vibrator connection pin
Vibrator connection pin
GND
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
FLASH XBSY input
GND
Flash data input and output
Power supply
Not used
Not used
Flash chip enable output
GND
FLAsh read enable output
Flash write enable output
Flash address latch enable output
Flash command latch enable output
Flash data input and output
GND
Not used
Not used
MS (FLASH) ROM/RAM setup input “L” : ROM, “H” : RAM (fixed at “H”)
Power supply
MS (FLASH) size setup input
Pin Name
CNUM
GND
SBS
NC (TAD9 to TAD8)
SDIO
NC (TAD7)
VDD
SCKI
GND
NC (TAD6 to TAD1)
WP
NC (TAD0)
NC (TST0 to TST1)
XRST
VDD
XO
XI
GND
NC
NC (TST2 to TST3)
NC (TALLEW)
NC (TBCE)
NC (TEECLK)
NC
NC (TMCLK)
NC (TSCLK)
NC (TXSCLK)
NC (TBOE)
XBSY
GND
MD7 to MD4
VDD
NC (TRST)
NC
XCE1 and XCE0
GND
XRE
XWE
ALE
CLE
MD3 to MD0
GND
LSI_TEST
DLY_XENA
XROM
VDD
CSIZE2 to CSIZE0
