38
NW-HD5
Pin No.
Pin Name
I/O
Description
169
MSINS
I
Card detection signal input from the memory stick interface Not used
170
P17
I
HOLD key detection signal input terminal "L": hold
171
P10/DADT
I
Audio data input from the memory stick interface Not used
172
P11/ADDT
I
Audio data input from the sub system controller
173
P12/LRCK
I
L/R sampling clock signal input from the sub system controller
174
P13/BCK
I
Bit clock signal input from the sub system controller
175
P14/FS256
O
Clock signal (11.2896 MHz) output to the multi interface
176
P15/MUTFGL
O
Not used
177
P15/MUTFGR
O
Not used
178
DVDD3
-
Power supply terminal (+1.2V) (for core)
179
DVSS5
-
Ground terminal
180
VDIO5
-
Power supply terminal (+1.9V) (for I/O interface)
181
PJ0/WAIT
I
Wait signal input from the multi interface
182
PJ1/RE
O
Read signal output to the multi interface
183
PJ2/LWR/LB
O
Write strobe signal output to the multi interface (lower byte)
184
PJ3/UWR/UB
O
Write strobe signal output to the multi interface (upper byte)
185
PJ4/WE
O
Write signal output to the multi interface
186
PK0/CS0
O
Chip select signal output to the flash memory
187
GAND_XCS1
O
Chip select signal output to the flash memory Used for the E, Taiwan, Korean, Chinese and
Tourist models
188
PK2/XBOOT
I
Boot mode selection signal input terminal Not used
189
PK3/MS_SIO
I
Boot mode selection signal input terminal Not used
190
PK4
I
Not used
191
PK5/CS5
O
Chip select signal output to the multi interface
192
PK6/CS6
O
Chip select signal output to the multi interface
193
PK7/CS7
O
Chip select signal output to the multi interface
194
DVSS6
-
Ground terminal
195
VDIO6
-
Power supply terminal (+1.9V) (for I/O interface)
196 to 207
PL0/A0 to PL7/A7,
PM0/A8 to PM3/A11
O
Address signal output to the flash memry and mullet interface
208
DVSS6
-
Ground terminal