Sony HCD-XGV11AV, Руководство по обслуживанию

Страница: 54 / 88

HCD-XGV11AV
54 54
7-32. IC PIN FUNCTIONS
1 VB O Not used (Connected to ground with capacitor)
2 IREF O Reference current output of DAC
3 VRF I Reference voltage input of DAC
4 VG O Not used (Connected to VDD with capacitor)
5 XCPSIG O Not used (Connected to ground)
6 CPSIG O Video composite/component (Y) signal output
7 NC O Video chroma (C) signal output (Not used )
8 NC — Connected to +2.5 V
9 V_AVS — Ground
10 IVD1 — Power supply (+3.3V)
11 I2C_CLK I/O Not used (open)
12 I2C_DATA I/O Not used (open)
13 GPIO0 I Serial data input from M30620
14 GPIO1 O Serial data output to M30620
15 GPIO2 I Serial clock input from M30620
16 GPIO3 I Data request signal input
17 LVD1 — Power supply (+2.5V)
18 GPIO4 O Ok signal output to M30620
19 GPIO5 I Chip select signal input from M30620
20 GPIO6 I Not used (open)
21 GPIO7 O Not used (open)
22 LVS1 — Ground
23 GPIO8 O Not used (open)
24 GPIO9 O Clock select signal output
25 GPIO10 O Not used (open)
26 GPIO11 O Latch signal output to PCM1748
27 LVD2 — Power supply (+2.5V)
28 GPIO12 O Data load signal output to BU2507FV
29 GPIO13 O Serial data output to BU2507FV
30 GPIO14 O Serial data clock output from BU2507FV
31 IVS1 — Ground
32 LVS2 — Ground
33 IVD2 — Power supply (+3.3V)
34 to 37 DRADR0 to 3 O Address output to memory
38 LVD3 — Power supply (+2.5V)
39 to 45 DRADR4 to 10 O Address output to memory
46 LVS3 — Ground
47 IVS3 — Ground
48 IVD3 — Power supply (+3.3V)
49 to 56 DRDAT0 to 7 I/O Data input/output to memory
57 IVS3 — Ground
58 IVD4 — Power supply (+3.3V)
59 to 66 GRDAT8 to 15 I/O Data and input/output to memory
67 IVS4 — Ground
68 DRCAS O CAS signal output to memory
69 LVD4 — Power supply (+2.5V)
70 DRCK O Clock output to memory
71 IVD5 — Power supply (+3.3V)
72 DRRAS O RAS signal output
73 DRWEL O Write enable signal output to memory
Description Pin Name Pin No. I/O
• IC505 CXD1887R CD-DSP, DIGITAL SERVO, MPEG DECODER, DAC (VIDEO board)
Description Pin Name Pin No. I/O
74 NVOEL O Out enable signal output to memory
75 LVS4 — Ground
76 DRBS O Bank select address output to memory
77 DRDQM0 O Lower byte mask of memory
78 DRDQM1 O Upper byte mask of memory
79 IV55 — Ground
80 NC — Not used (open)
81 SYSRST I System reset signal input
82 IRDIN I Not used (Connected to ground)
83 NC — Not used (open)
84 VDD1 — Power supply (+2.5V)
85 V16M I/O Not used (open)
86 DOUT O Digital audio data output (Not used)
87 L_CDLRCK I D/A interface, L/R clock input
88 LRCK O D/A interface, L/R clock output
89 VSS1 — Ground
90 L_CDDATA I Serial data input from D/A interface
91 PCMD O Serial data output to D/A interface
92 L_CDBCK I Bit clock input (2’s COMP) from D/A interface
93 BCK O Bit clock output (2’s COMP) to D/A interface
94 EMPH O Not used (open)
95 L_SQSO I SubQ 80bit and PCM peak level data input
96 SQSO O SubQ 80bit and PCM peak level data output
97 VDD2 — Power supply (+2.5V)
98 L_SQCK O SQSO read out clock output
99 SQCK I SQSO read out clock input
100 SBSO O Not used (open)
101 EXCK I Not used (Connected to ground)
102 DATA I Serial data input from CPU
103 L_DATA O Serial data output to CPU
104 VSS2 — Ground
105 L_CDXRST I System reset signal input (L:reset)
106 XRST O System reset signal output (L:reset)
107 MUTE I Not used (Connected to ground)
108 L_XLAT O Latch signal output to CPU
109 XLAT I Latch signal input from CPU
110 L_DCLK O Serial data clock output
111 CLOK I Serial data clock input
112 L_SENS I SENS signal input
113 SENS O SENS signal output
114 L_SCLK O SENS serial data read clock output
115 SCLK I SENS serial data read clock input
116 VDD3 — Power supply (+2.5V)
117 ATSK I/O Not used (Connected to ground)
118 XUGF O Not used (open)
119 XPCK O Not used (open)
120 L_GFS I GPS signal input
121 GFS O GPS signal output
122 VSS3 — Ground