56
1
PIO [10:0]
I/O
Programmable I/O pins.
2 to 4
HDATA [7:0]
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
5
VDD
—
3.3-V supply voltage for core logic and I/O signals.
6
HDATA [7:0]
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
7
VSS
—
Ground for core logic and I/O signals.
8 to 11
HDATA [7:0]
I/O
8 bit bl-directional host data bus. Host writes data to the decoder Code FIFO via
HDATA [7:0]. MSB of the 32-bit word is written first. The host also reads and writes
the decoder internal registers and local SDRAM/ROM via HDATA [7:0].
12
VDD
—
3.3-V supply voltage for core logic and I/O signals.
13
RESET
I
Hardware reset. An external device asserts RESET (active LOW) to execute a
decoder hardware reset. To ensure proper initialization after power in stable, assert
RESET for at least 20 Ms.
14
VSS
—
Ground for core logic and I/O signals.
15
WAIT
O
Active LOW to indicate host initiated transfer is not complete. WAIT is asserted after
the falling edge of CS and reasserted when decoder is ready to complete transfer cycle.
Open drain signal, must be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.
16
INT
O
Host interrupt. Open drain signal, must be pulled-up to 3.3 volts. Driven high for
10 ns before tristate.
17
VDD
—
3.3-V supply voltage for core logic and I/O signals.
19
VSS
—
Ground for core logic and I/O signals.
27
VDD
—
3.3-V supply voltage for core logic and I/O signals.
29
VSS
—
Ground for core logic and I/O signals.
36
VDD
—
3.3-V supply voltage for core logic and I/O signals.
38
VSS
—
Ground for core logic and I/O signals.
40
VDD
—
3.3-V supply voltage for core logic and I/O signals.
42
VSS
—
Ground for core logic and I/O signals.
47
VDD
—
3.3-V supply voltage for core logic and I/O signals.
49
VSS
—
Ground for core logic and I/O signals.
52
PIO [10:0]
I/O
Programmable I/O pins.
53, 54
MDATA [15:0]
I/O
Memory address.
55
VDD
—
3.3-V supply voltage for core logic and I/O signals.
56
MDATA [15:0]
I/O
Memory address.
57
VSS
—
Ground for core logic and I/O signals.
58 to 60
MDATA [15:0]
I/O
Memory address.
61
VDD
—
3.3-V supply voltage for core logic and I/O signals.
62
MDATA [15:0]
I/O
Memory address.
63
VSS
—
Ground for core logic and I/O signals.
64
MDATA [15:0]
I/O
Memory address.
65
VDD
—
3.3-V supply voltage for core logic and I/O signals.
66
MDATA [15:0]
I/O
Memory address.
67
VSS
—
Ground for core logic and I/O signals.
68
MDATA [15:0]
I/O
Memory address.
69
VDD
—
3.3-V supply voltage for core logic and I/O signals.
70
MDATA [15:0]
I/O
Memory address.
71
VSS
—
Ground for core logic and I/O signals.
72 to 74
MDATA [15:0]
I/O
Memory address.
75
VDD
—
3.3-V supply voltage for core logic and I/O signals.
Pin No.
Pin Name
I/O
Function
• IC506 MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR (CL8830-PD0) (VIDEO BOARD (2/2))