– 103 –
Pin No.
Pin Name
I/O
Function
• IC502 MPEG DECODER, MECHANISM CONTROL (M30620MC-A05FP) (VIDEO Board (1/3))
1
SENSE
I
Internal state (SENSE) monitor input (IC101)
2
SENSE CLK
O
Serial data reading clock output (IC101)
3
DSP DATA
O
Serial data output (IC101)
4
DSP LATCH
O
Lach output (IC101)
5
DSP CLK
O
Serial data clock output (IC101)
6
TSENS
I
Not used
7
REMOTE IN
I
Not used
8
BYTE
I
External bus width change input (Connected to ground)
9
VSS
–
Ground
10
DSP MUTE
O
Mute output (IC101) “H” : mute
11
CTRL1 (L : DOUBLE)
O
Double change output (IC101) “L” : double
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input (10MHz)
16
VCC
–
+5V power supply
17
NMI
I
Requests mask disable interruption input (Connected to +5V)
18
SCOR
I
Subcode sync input (IC101)
19
D SENS
I
Not used
20
CL680 INT
I
Video CD interruption input (IC505)
21
CL680 HSEL
O
Video CD select data of the host MPU (IC505)
22
DF LATCH
O
Digital filter latch output (IC509)
23
CL680 HRDY
I
Ready signal input for communication to the host MPU (IC505)
24
680 RESET
O
Video CD reset output (IC505) “L” : reset
25
JOG1
I
Not used
26
JOG2
I
Not used
27
CTRL2
O
Double control output (IC101) “H” : double
28
LD ON
O
Laser diode ON/OFF output
29
IIC1
I/O
IIC clock input from master control
30
IIC0
I/O
IIC data input from master control
31
DATA1O
O
Serial 1 data output (IC505, 509)
I
Serial 1 data input (IC505, 509)
O
Serial 1 clock output
O
Sharpness output L : normal, H : sharpness
O
Fix the video signal output level output
I
Serial 2 data input for subcode sync reading
I
Serial 2 clock input for subcode sync reading
I
Not used
I
Not used
I
Not used
I
Not used
42, 43
BUS
I
Not used
44
BUS XRD
I
Model selection input “L” : chinese model, “H” : except chinese model
45
BUS
I
V sync signal input
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