Sony HCD-MJ1, Руководство по обслуживанию

Страница: 27 / 68

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Pin No. Pin name I/O Description
50 VSS – Ground terminal.
51 VDD – Power supply terminal. (+5V)
52– 55 A03– A00 O Address signal output to the RAM (IC222)
56– 60 A04– A08 O Address signal output to the RAM (IC222)
61 XOE O Output enable control signal output to the RAM (IC222).
62 XCAS O Column address strobe signal output to the RAM (IC222).
63 VSS – Ground terminal.
64 XCS O Chip select signal output. Not used this set
65 A09 O Address signal output to the RAM (IC222).
66 XRAS O Row address strobe signal output to the RAM (IC222).
67 XWE O Write enable control signal output to the RAM (IC222).
68,69 D1, D0 I/O RAM (IC222) data bus.
70,71 D2,D3 I/O RAM (IC222) data bus.
72–74 D4–D6 I/O Data bus. Not used this set (OPEN)
75 VSS – Ground terminal.
76 D7 I/O Data bus. Not used this set (OPEN)
77 ERR I/O
Input/output terminal of the error (C2PO) data signal to the external RAM.
Not used this set (OPEN)
78 EXTC2R I
External RAM selection signal input for the error data writing.
(When “H” : External RAM) (Fixed at “L”).
79 BUSY O BUSY signal output of the RAM access. Not used this set (OPEN)
80 EMP O Empty or before the full of the ATRAC data. (When DSC=ASC+1 : “H” ). Not used this set.
81 FUL O Full or before the empty of the ATRAC data. (When ASC=DSC+1 : “H” ). Not used this set.
82 EQL O Empty of the ATRACK data. (when DSC=ASC : “H” ). Not used this set.
83 MDLK O
Indicate the main/sub of the recording or playback data.
(When sub and linking : “H” , When the main : “L”). Not used this set.
84 CPSY O Interpolation sync signal output. Not used this set.
85 CTMD0 O DSC counter mode output. Not used this set.
86 CTMD1 O DSC counter mode output. Not used this set.
87 SPO O System clock (512Fs=22.5792MHz) signal output to CXD2535BR (IC121).
88 VSS – Ground terminal.
89 MDSY O Sync detection signal output of the main data. Not used this set.
90 LRCK I L/R clock (44.1kHz) signal input from CXD2535BR (IC121).
91 BCK I Bit clock (2.8224MHz) signal input from CXD2535BR (IC121).
C2PO (indicate the error mode of the data) signal input from CXD2535BR (IC121).
92 C2PO I When playback : C2PO (“H”), When digital recording : D. IN-Vflag,
When analog recording : “L”
When recording : Record audio data signal output to CXD2535BR (IC121).
93 DATA I/O
When playback : playback audio data signal input from CXD2535BR (IC121).
94 DIDT I 16-bit data input terminal for the digital audio in from the CXD2535BR(IC121).
95 DODT O 16-bit data output terminal for the digital audio out from the CXD2535BR (IC121).
96 DIRCPB O
Disc drive, Record or playback mode output of the EFM encoder/decoder.
Not used this set (Open)
97 MIN I Defect ON/OFF selection signal input from CXD2535BR (IC121).
98 SPOSL I IN/OUT selection input terminal of the pin
*¶
. ( “L” : IN, “H” : OUT) (Fixed at “H”)
99 MCKT1 O Internal master clock signal output terminal of the RAM controller. Not used ths set.
100 VSS – Ground terminal.