HCD-EH15
26
PANEL BOARD IC701 MB90F830PF-GE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
LED
O
LED drive signal output terminal for liquid crystal display back light "H": LED on
2
CD OPEN/CLOSE
I
CD lid open/close detection switch input terminal "L": CD lid is closed
3
REQ
I
Request signal input from the CD-MP3 processor
4
MMUT
O
Muting signal output to the coil/motor driver
5 to 8
BUS0 to BUS3
O
Serial data output to the CD-MP3 processor
9
RMC
I
Remote control signal input from the remote control receiver
10
BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
11
XCCEN
O
Chip enable signal output to the CD-MP3 processor
12
XRST
O
Reset signal output to the CD-MP3 processor "L": reset
13
X2
I
Sub system clock input terminal (32.768 kHz)
14
X3
O
Sub system clock output terminal (32.768 kHz)
15
VCC
-
Power supply terminal (+3.3V)
16
VSS
-
Ground terminal
17 to 21
NC
-
Not used
22
LED_STBY
O
LED drive signal output terminal for STANDBY indicator "L": LED on
23
CD_ON
O
Power supply on/off control signal output terminal for CD section "H": power on
24
NC
-
Not used
25
TU_DO
I
Serial data input from the FM/AM tuner
26
RDA_DATA
I
RDS serial data input from the RDS decoder (UK model only)
27 to 31
NC
-
Not used
32
AVCC
-
Power supply terminal (+3.3V)
33
FUNC_SDA
O
Serial data output to the electrical volume
34
AMP_ON
O
Standby control signal output to the power ampli
fi
er "L": standby
35
AVSS
-
Ground terminal
36
P_MONI
I
Power monitor input terminal
37, 38
KEY1, KEY2
I
Front panel key input terminal (A/D input)
39
TU_ASD
I
Auto gain control signal input from the FM/AM tuner
40
TP_STATE
I
REC/PB detection signal input terminal
41
KEY0
I
Power key input terminal
42
HOLD
I
Hold signal input terminal
43
SBSY
I
Subcode block sync signal input from the CD-MP3 processor
44
VSS
-
Ground terminal
45
RDS_CLK
I
RDS serial data transfer clock signal input from the RDS decoder (UK model only)
46
POWER_ON
O
Main power supply on/off control signal output terminal "H": power on
47
SUFIX
I
Destination setting terminal
48
RE_VOL
I
Jog dial pulse input from the rotary encoder (for VOLUME)
49, 50
NC
-
Not used
51
MD2
I
Mode setting terminal Fixed at "L" in this set
52, 53
MD1, MD0
I
Mode setting terminal Fixed at "H" in this set
54
RESET
I
Reset signal input terminal "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
55
TU_CE
O
Chip enable signal output to the FM/AM tuner
56
TU_CLK
O
Serial data transfer clock signal output to the FM/AM tuner
57
TU_DI
O
Serial data output to the FM/AM tuner
58
V3
-
Terminal for doubler circuit capacitor connection to develop liquid crystal display drive volt-
age
59 to 62
COM0 to COM3
O
Common drive signal output to the liquid crystal display
63, 64
SEG0, SEG1
O
Segment drive signal output to the liquid crystal display
65
VCC
-
Power supply terminal (+3.3V)
66
VSS
-
Ground terminal
67 to 89
SEG2 to SEG24
O
Segment drive signal output to the liquid crystal display
90
VCC
-
Power supply terminal (+3.3V)
91
VSS
-
Ground terminal
92
X1
I
Main system clock output terminal (5.53 MHz)
93
X0
O
Main system clock input terminal (5.53 MHz)
94 to 100
SEG25 to SEG31
O
Segment drive signal output to the liquid crystal display