Sony ExwaveHAD SSC-DC50A, Руководство по обслуживанию

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3-1 SSC-DC50A/54A
SSC-DC50AP/54AP/58AP
SECTION 3
OPERATIONAL DESCRIPTION
3-1. BI-135 BOARD
The signal (IC101 pin 10) output from the CCD imager
(IC101) passes through the buffer (Q101), and it is output
to the PR-229 board from CN101 pin 2. H1, H2, and V1,
V2, V3, V4 pulses are CCD drive pulses supplied from the
PR-229 board.
3-2. PR-229 BOARD
(1) Main signal processing circuits
The CCD-OUT signal (CN202 pin 13) from the BI-135
board is input to IC203 pins 25 and 26, then it is subjected
to the correlative double sampling (CDS), and further it is
amplified in the AGC circuit and output from the pin 8.
Then, it is input to the IC209 pin 39, and A/D conversion
is executed.
10 bits of A/D output (IC209 pins 1-5, 8-12) are input to the
DSP CORE signal processing circuit (IC212 pins 94-85).
After digital signal processing, D/A conversion is
executed, and analog Y and C output signals are attained
(IC212 pin 20: Y, pin 21: C).
These Y and C signals pass through the filters respectively
(FL202: Y, FL201: C), then they are added, passed through
amplifier (IC226), and output from CN203 pin 10 and 12.
(2) Microcomputer peripheral circuits
The microcomputer (IC217) sets all parameters for digital
signal processing circuit (in IC212), and saves some data
in the E 2 PROM (IC215).
Also, it makes a digital control of analog data through D/A
converter (IC210).
(3) CCD drive pulse signal circuits
Receiving main clock of 28 MHz, the timing generator
(IC206) generates the CCD drive pulses and the pulses for
sample hold.
Also, a synchronizing signal necessary for the timing
generator is got from the sync. signal generator in the IC212.
(4) External Synchronizing circuits
This camera can operate with the VBS/VS sync and MPX-
VS sync [SSC-DC50A/50AP] or LL sync [SSC-DC54A/
54AP/58AP] .
(VBS) A burst signal is extracted from the sync
source VBS signal entered from CN203-14
pin to detect whether a burst is present or not
(VBS or VS). If a burst signal is detected. It
is entered to the IC212-61 pin. The output of
phase comparison with internal subcarrier
(IC212-47 pin) is reflected to the internal
subcarrier VCXO (near X203) through LPF at
the IC219 periphery. Also, sync source signal
is entered to the IC212-60 pin to comprise
VReset/H-PLL. Sync detection is done by
IC232.
(VS) Sync source VS signal from CN203-14 pin is
entered to the IC212-60 pin to comprise
VReset/H-PLL. This H phase comparison
output (IC212-63 pin) is reflected to the LC
type VCO for internal master (in the vicinity
of IC208) through LPF at the IC227
periphery. Sync detection is done by IC232.
(MPX-VS) Sync source VS signal separated from the
superposed line in the PS-477 board is got
from CN203-14 pin.
This signal is processed in the same manner as
(VS).
(LL) V pulse (line frequency sync) from CN203-16
pin is entered to the IC212-61 pin. This V
pulse and internal VD comprise PLL. This V
phase comparison output (IC212-63 pin) is
reflected to the LC type VCO for internal
master (in the vicinity of IC208) through LPF
at the IC227 periphery.
(5) VS servo circuit
This circuit controls the gain (IC201-2 pin) of VS signal
(IC201-3 pin) for lens drive via EVR under control of the
microcomputer (IC212).
3-3. PS-477 BOARD
(1) Power supply circuit
Using DC 12 V from the power input terminal or DC
voltage (28 V typ) separated from the superposed line, the
DC-DC converter and series regulator (IC804) generate 3.3
V, 5 V, 9 V, 15 V, and –9 V.
(2) Superposed circuit
In this circuit, the camera video (IC602 pin 1) is
superposed with the superposed line (CN801 pin 10) and
also a low pass filter is composed so as to take DC voltage
and to supply it to the power circuit.
Then, the external sync. pulse is separated at a differential
operation circuit.
The selector (IC 802) switches the superposed sync. signal
and VBS/VS signal.