Sony CX-VX55, Руководство по обслуживанию

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66
CX-VX55/VX77
Ver. 1.1
Pin No. Pin Name I/O Pin Description
57 IO_VSS — I/O digital ground
58 PWM4_M O Negative PWM output of channel 4.
59 PWM4_P O Positive PWM output of channel 4.
60 IO_VSS — I/O digital ground
61 PWM5_M O Negative PWM output of channel 5.
62 PWM5_P O Positive PWM output of channel 5.
63 DVSS — Core digital ground
64 IO_VSS — I/O digital ground
65 IO_VDD — I/O digital power supply (+3.3 V)
66 DVDD — Core digital power supply (+2.5 V)
67 PWM6_M O Negative PWM output of channel 6.
68 PWM6_P O Positive PWM output of channel 6.
69 IO_VSS — I/O digital ground
70 PWM7_M O Negative PWM output of channel 7. (Not used in this set)
71 PWM7_P O Positive PWM output of channel 7. (Not used in this set)
72 IO_VDD — I/O digital power supply (+3.3 V)
73 IO_VSS — I/O digital ground
74 PWM8_M O Negative PWM output of channel 8. (Not used in this set)
75 PWM8_P O Positive PWM output of channel 8. (Not used in this set)
76 OVERLOAD I Power stage overload indication input
77 EPD_ENA O External amplifier power device enable output (H: active)
78 SO/SDA I/O SO for SPI mode signal input/output or SDA for I2C mode signal input/output.
79 SCK/SCL I SCK for SPI mode signal input or SCL for I2C mode signal input.
80 DVDD — Core digital power supply (+2.5 V)
81 DVSS — Core digital ground
82 SI/I2C_AD0 I
SI for SPI mode signal input or slave address 0 for I2C mode signal input.
(Fixed at H in this set)
83 /CS/I2C_AD2 I
Chip selector for SPI mode signal input or slave address 2 for I2C mode signal input.
(Fixed at H in this set)
84 SPI/I2C I Host interface mode (SPI or I2C) select signal input (Fixed at L in this set)
85 IO_VSS — I/O digital ground
86 CLK_IN I External clock input (12.288MHz)
87 IO_VDD — I/O digital power supply (+3.3 V)
88 DMIX_LRCK O PCM word clock (left-right clock) output of downmix signal. (Not used in this set)
89 DMIX_BCK O PCM bit clock output of downmix signal. (Not used in this set)
90 DMIX_SDOUT O PCM serial data output of downmix signal. (Not used in this set)
91 DVDD — Core digital power supply (+2.5 V)
92 DVSS — Core digital ground
93 DMIX_MCLK O Main clock output for external downmix line output D/A converter. (Not used in this set)
94 IO_VDD — I/O digital power supply (+3.3 V)
95 IO_VSS — I/O digital ground
96 /RESET I H/W reset signal input (L: active)
97, 98
TEST_MODE1,
I Test mode selection pin 1, 2 (Not used in this set)
TEST_MODE2
99 SCAN_ENA I Scan enable signal input (H: active) (Not used in this set)
100 TEST_MODE3 I Test mode selection pin 3 (Not used in this set)