Sony CMT-EX5 - Micro Hi Fi Component System, Руководство по обслуживанию

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43
HCD-EX5
• IC701
µ
PD703030BYGF-M02-3BA Master Controller (Main Board)
6-17. IC Pin Function Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31, 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
I/O
O
O
I/O
O
I/O
I
O
O
—
—
O
O
O
I
I
O
O
O
O
O
—
O
O
I
O
O
O
O
O
O
O
O
I
I
O
—
O
I
—
—
O
O
I
O
O
O
I
I
I
O
Pin Name
DISP_DATA
DISP_CLK
IIC DATA
DACLAT
IIC CLK
CD_ADJ
CXD-DATA
CXD-CLK
EVDD
EVSS
CXD-XLT
PWM1
LDON
SENSE
SUBQ
SOFT_CHEK_1
SQCLK
SOFT_CHECK_2
PWM2
PWM3
VPP
BDPWR
BDRST
HP_IN
HP_MUTING
SPK-RELAY
HP MUTE
DIG-AMP-SLEEP
GEQ-DATA
GEQ-CLK
DIM0, DIM1
LINE-MUTING
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
PLL-CLK
PLL-DI(ST
p
UCOM)
PLL-DO(UCOM
p
ST)
PLL-CE
ST-MUTING
STEREO
TUNED
RDS-DATA
AM
Description
Data output to the LCD601
Clock output to the LCD601
IIC data input/output (fixed at “H”)
Latch signal output to the DAC (IC301)
IIC clock input/output (fixed at “H”)
CD adjustment mode input (fixed at “H”)
Data output to the CXD3068Q (IC101)
Clock output to the CXD3068Q (IC101)
Power supply (+5V)
Ground
Latch signal output to the CXD3068Q (IC101)
PWM1 signal output
Laser power control signal output
SENSE signal input from the CXD3068Q (IC101)
SUBQ data input from the CXD3068Q (IC101)
Check terminal (open)
SUBQ clock output to the CXD3068Q (IC101)
Check terminal (open)
PWM2 signal output
PWM3 signal output
Internal connection/power for writing to the flash ROM
BD power control signal output
BD reset signal output
Headphone detection signal input
Not used (open)
Speaker relay control signal output
PC/TAPE/MD output muting signal output
Sleep signal output to the digital power amplifier (IC101)
Data output to the pre-amplifier (IC121)
Clock output to the pre-amplifier (IC121)
Back light control signal output
Line muting signal output
System reset signal input
Sub clock input
Sub clock output
Capacitor terminal for stabilizing the regulator output
Main clock output
Main clock input
Ground
Power supply (+5V)
Clock output terminal (open)
Clock output for the PLL for the tuner
Data input from the PLL for the tuner
Data output to the PLL for the tuner
Chip enable signal output the PLL for the tuner
Muting signal output for the tuner
Stereo detection signal input
Tuner tuning signal input
RDS data input
AM signal output for the RDS noise reduction