33
CDX-747X
Pin No.
Pin Name
I/O
Description
47, 48
MD0, MD1
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
49
MD2
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
50
EJECT SW
I
Eject switch (SW801) input terminal “L” active
51
MAGLK SW
I
Magazine detect switch (SW201) input terminal “L”: magazine is set
52
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3027R (IC101)
53
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the D-RAM controller section on the
CXD3027R (IC101)
54
NC
O
Not used (open)
55
HS
O
Normal/high speed playback control signal output terminal
“L”: high speed playback Not used (open)
56
SQSO
I
Subcode Q data input from the CXD3027R (IC101)
57
NC
O
Not used (open)
58
SQCK
O
Subcode Q data reading clock signal output to the CXD3027R (IC101)
59
CDCLK
O
Serial data transfer clock signal output to the CXD3027R (IC101)
60
CDLAT
O
Serial data latch pulse signal output to the CXD3027R (IC101)
61
CDDAT
O
Serial data output to the CXD3027R (IC101)
62
XRST
O
System reset signal output to the CXD3027R (IC101) and D/A converter (IC501) “L”: reset
63
XQOK
O
Subcode Q OK pulse signal output to the CXD3027R (IC101) “L” active
64
XRDE
O
D-RAM read enable signal output to the CXD3027R (IC101) “L” active
65
XWRE
O
D-RAM write enable signal output to the CXD3027R (IC101) “L” active
66
EMPH
O
Emphasis control signal output to the D/A converter (IC501) “H”: emphasis on
67
MUTE
O
Audio line muting on/off control signal output “H”: muting on
68
RAMA10
O
Address signal output to the S-RAM Not used (open)
69
RAMCS
O
Chip select enable output to the S-RAM Not used (open)
70 to 74
RAMIO7 to
RAMIO3
I/O
Two-way data bus with the S-RAM Not used (open)
75
RESET
I
System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC303)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
76
RAMIO2
I/O
Two-way data bus with the S-RAM Not used (open)
O
Sub system clock output terminal Not used (open)
I
Sub system clock input terminal Not used (fixed at “L”)
—
Ground terminal
I
Main system clock input terminal (4 MHz)
O
Main system clock output terminal (4 MHz)
—
Power supply terminal (+3.3V)
Two-way data bus with the S-RAM Not used (open)
O
Address signal output to the S-RAM Not used (open)
89
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode (fixed at “H”)
90
DOUTSEL
I
Analog/digital select switch input terminal Not used (open)
91
CFSEL
I
Custom file on/off setting terminal “L”: custom file on (fixed at “L”)
92
TEXTSEL
I
CD text mode setting terminal
“L”: CD text on, “H”: does not display track name (fixed at “L”)
93
ESPSEL
I
ESP on/off setting terminal “L”: ESP on (fixed at “L”)
94
TEST
I
Test mode setting terminal “L”: test mode Not used (open)
95
MAG SW
I
Magazine in/out detect switch input terminal Not used (open)
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